5050pwm.map.qmsg

FPGA 实现基于ISA接口的3路编码器计数

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 07 15:29:53 2008 " "Info: Processing started: Mon Jul 07 15:29:53 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off 5050PWM -c 5050PWM " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 5050PWM -c 5050PWM" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "5050PWM.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file 5050PWM.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 5050PWM " "Info: Found entity 1: 5050PWM" {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "5050PWM_V22.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file 5050PWM_V22.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 5050PWM_V22 " "Info: Found entity 1: 5050PWM_V22" {  } { { "5050PWM_V22.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM_V22.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "5050PWM_V23.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file 5050PWM_V23.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 5050PWM_V23 " "Info: Found entity 1: 5050PWM_V23" {  } { { "5050PWM_V23.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM_V23.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "5050PWM_V24.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file 5050PWM_V24.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 5050PWM_V24 " "Info: Found entity 1: 5050PWM_V24" {  } { { "5050PWM_V24.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM_V24.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "5050PWM_V30.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file 5050PWM_V30.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 5050PWM_V30 " "Info: Found entity 1: 5050PWM_V30" {  } { { "5050PWM_V30.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM_V30.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "5050PWM_V31.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file 5050PWM_V31.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 5050PWM_V31 " "Info: Found entity 1: 5050PWM_V31" {  } { { "5050PWM_V31.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM_V31.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "5050PWM_V32.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file 5050PWM_V32.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 5050PWM_V32 " "Info: Found entity 1: 5050PWM_V32" {  } { { "5050PWM_V32.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM_V32.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "5050PWM_V38.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file 5050PWM_V38.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 5050PWM_V38 " "Info: Found entity 1: 5050PWM_V38" {  } { { "5050PWM_V38.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM_V38.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "5050PWM_V41.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file 5050PWM_V41.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 5050PWM_V41 " "Info: Found entity 1: 5050PWM_V41" {  } { { "5050PWM_V41.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM_V41.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "5050PWM_V42.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file 5050PWM_V42.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 5050PWM_V42 " "Info: Found entity 1: 5050PWM_V42" {  } { { "5050PWM_V42.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM_V42.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "5050PWM_V50.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file 5050PWM_V50.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 5050PWM_V50 " "Info: Found entity 1: 5050PWM_V50" {  } { { "5050PWM_V50.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM_V50.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "5050PWM " "Info: Elaborating entity \"5050PWM\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 936 360 592 1192 "inst5" "" } { 936 360 592 1192 "inst5" "" } { 936 360 592 1192 "inst5" "" } { 936 360 592 1192 "inst5" "" } { 936 360 592 1192 "inst5" "" } } } }  } 0 0 "Found multiple base names" 0 0}
{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 936 360 592 1192 "inst5" "" } { 936 360 592 1192 "inst5" "" } { 936 360 592 1192 "inst5" "" } { 936 360 592 1192 "inst5" "" } { 936 360 592 1192 "inst5" "" } } } }  } 0 0 "Found multiple base names" 0 0}
{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 936 360 592 1192 "inst5" "" } { 936 360 592 1192 "inst5" "" } { 936 360 592 1192 "inst5" "" } { 936 360 592 1192 "inst5" "" } { 936 360 592 1192 "inst5" "" } } } }  } 0 0 "Found multiple base names" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D8 74377 inst4 " "Warning: Port \"D8\" of type 74377 and instance \"inst4\" is missing source signal" {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 656 200 304 848 "inst4" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D7 74377 inst4 " "Warning: Port \"D7\" of type 74377 and instance \"inst4\" is missing source signal" {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 656 200 304 848 "inst4" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D2 74377 inst4 " "Warning: Port \"D2\" of type 74377 and instance \"inst4\" is missing source signal" {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 656 200 304 848 "inst4" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D6 74377 inst4 " "Warning: Port \"D6\" of type 74377 and instance \"inst4\" is missing source signal" {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 656 200 304 848 "inst4" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D3 74377 inst4 " "Warning: Port \"D3\" of type 74377 and instance \"inst4\" is missing source signal" {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 656 200 304 848 "inst4" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D4 74377 inst4 " "Warning: Port \"D4\" of type 74377 and instance \"inst4\" is missing source signal" {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 656 200 304 848 "inst4" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D5 74377 inst4 " "Warning: Port \"D5\" of type 74377 and instance \"inst4\" is missing source signal" {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 656 200 304 848 "inst4" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "pwm.bdf 1 1 " "Warning: Using design file pwm.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 pwm " "Info: Found entity 1: pwm" {  } { { "pwm.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/pwm.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm pwm:inst " "Info: Elaborating entity \"pwm\" for hierarchy \"pwm:inst\"" {  } { { "5050PWM.bdf" "inst" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 368 632 744 528 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_dff0.vhd 2 1 " "Warning: Using design file lpm_dff0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_dff0-SYN " "Info: Found design unit 1: lpm_dff0-SYN" {  } { { "lpm_dff0.vhd" "" { Text "D:/FPGA/5050PWM_V54/lpm_dff0.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_dff0 " "Info: Found entity 1: lpm_dff0" {  } { { "lpm_dff0.vhd" "" { Text "D:/FPGA/5050PWM_V54/lpm_dff0.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}