5050pwm.hier_info

FPGA 实现基于ISA接口的3路编码器计数

Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst7|74377b:inst6|enadff:3
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst7|74377b:inst6|enadff:2
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst7|74377b:inst6|enadff:18
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst7|74377b:inst6|enadff:19
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst7|74377b:inst6|enadff:24
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst7|74377b:inst6|enadff:25
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst7|74377b:inst7
Q4 <= enadff:15.Q
EN => 6.IN0
D4 => enadff:15.D
CLK => enadff:15.CLK
CLK => enadff:10.CLK
CLK => enadff:3.CLK
CLK => enadff:2.CLK
CLK => enadff:18.CLK
CLK => enadff:19.CLK
CLK => enadff:24.CLK
CLK => enadff:25.CLK
Q3 <= enadff:10.Q
D3 => enadff:10.D
Q2 <= enadff:3.Q
D2 => enadff:3.D
Q1 <= enadff:2.Q
D1 => enadff:2.D
Q5 <= enadff:18.Q
D5 => enadff:18.D
Q6 <= enadff:19.Q
D6 => enadff:19.D
Q7 <= enadff:24.Q
D7 => enadff:24.D
Q8 <= enadff:25.Q
D8 => enadff:25.D


|5050PWM|pwm:inst7|74377b:inst7|enadff:15
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst7|74377b:inst7|enadff:10
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst7|74377b:inst7|enadff:3
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst7|74377b:inst7|enadff:2
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst7|74377b:inst7|enadff:18
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst7|74377b:inst7|enadff:19
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst7|74377b:inst7|enadff:24
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst7|74377b:inst7|enadff:25
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst8
AEB <= lpm_dff0:inst.q
CLK => lpm_counter0:inst11.clock
WR => 74377b:inst6.CLK
WR => 74377b:inst7.CLK
CS0 => 74377b:inst6.EN
D[0] => 74377b:inst6.D[1]
D[0] => 74377b:inst7.D[1]
D[1] => 74377b:inst6.D[2]
D[1] => 74377b:inst7.D[2]
D[2] => 74377b:inst6.D[3]
D[2] => 74377b:inst7.D[3]
D[3] => 74377b:inst6.D[4]
D[3] => 74377b:inst7.D[4]
D[4] => 74377b:inst6.D[5]
D[4] => 74377b:inst7.D[5]
D[5] => 74377b:inst6.D[6]
D[5] => 74377b:inst7.D[6]
D[6] => 74377b:inst6.D[7]
D[6] => 74377b:inst7.D[7]
D[7] => 74377b:inst6.D[8]
D[7] => 74377b:inst7.D[8]
CS1 => 74377b:inst7.EN
clock => lpm_dff0:inst.clock


|5050PWM|pwm:inst8|lpm_dff0:inst
clock => lpm_ff:lpm_ff_component.clock
data => lpm_ff:lpm_ff_component.data[0]
q <= lpm_ff:lpm_ff_component.q[0]


|5050PWM|pwm:inst8|lpm_dff0:inst|lpm_ff:lpm_ff_component
data[0] => dffs[0].DATAIN
clock => dffs[0].CLK
enable => dffs[0].ENA
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sload => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE


|5050PWM|pwm:inst8|lpm_compare1:inst18
dataa[0] => lpm_compare:lpm_compare_component.dataa[0]
dataa[1] => lpm_compare:lpm_compare_component.dataa[1]
dataa[2] => lpm_compare:lpm_compare_component.dataa[2]
dataa[3] => lpm_compare:lpm_compare_component.dataa[3]
dataa[4] => lpm_compare:lpm_compare_component.dataa[4]
dataa[5] => lpm_compare:lpm_compare_component.dataa[5]
dataa[6] => lpm_compare:lpm_compare_component.dataa[6]
dataa[7] => lpm_compare:lpm_compare_component.dataa[7]
dataa[8] => lpm_compare:lpm_compare_component.dataa[8]
dataa[9] => lpm_compare:lpm_compare_component.dataa[9]
dataa[10] => lpm_compare:lpm_compare_component.dataa[10]
dataa[11] => lpm_compare:lpm_compare_component.dataa[11]
datab[0] => lpm_compare:lpm_compare_component.datab[0]
datab[1] => lpm_compare:lpm_compare_component.datab[1]
datab[2] => lpm_compare:lpm_compare_component.datab[2]
datab[3] => lpm_compare:lpm_compare_component.datab[3]
datab[4] => lpm_compare:lpm_compare_component.datab[4]
datab[5] => lpm_compare:lpm_compare_component.datab[5]
datab[6] => lpm_compare:lpm_compare_component.datab[6]
datab[7] => lpm_compare:lpm_compare_component.datab[7]
datab[8] => lpm_compare:lpm_compare_component.datab[8]
datab[9] => lpm_compare:lpm_compare_component.datab[9]
datab[10] => lpm_compare:lpm_compare_component.datab[10]
datab[11] => lpm_compare:lpm_compare_component.datab[11]
AgeB <= lpm_compare:lpm_compare_component.AgeB


|5050PWM|pwm:inst8|lpm_compare1:inst18|lpm_compare:lpm_compare_component
dataa[0] => cmpr_deg:auto_generated.dataa[0]
dataa[1] => cmpr_deg:auto_generated.dataa[1]
dataa[2] => cmpr_deg:auto_generated.dataa[2]
dataa[3] => cmpr_deg:auto_generated.dataa[3]
dataa[4] => cmpr_deg:auto_generated.dataa[4]
dataa[5] => cmpr_deg:auto_generated.dataa[5]
dataa[6] => cmpr_deg:auto_generated.dataa[6]
dataa[7] => cmpr_deg:auto_generated.dataa[7]
dataa[8] => cmpr_deg:auto_generated.dataa[8]
dataa[9] => cmpr_deg:auto_generated.dataa[9]
dataa[10] => cmpr_deg:auto_generated.dataa[10]
dataa[11] => cmpr_deg:auto_generated.dataa[11]
datab[0] => cmpr_deg:auto_generated.datab[0]
datab[1] => cmpr_deg:auto_generated.datab[1]
datab[2] => cmpr_deg:auto_generated.datab[2]
datab[3] => cmpr_deg:auto_generated.datab[3]
datab[4] => cmpr_deg:auto_generated.datab[4]
datab[5] => cmpr_deg:auto_generated.datab[5]
datab[6] => cmpr_deg:auto_generated.datab[6]
datab[7] => cmpr_deg:auto_generated.datab[7]
datab[8] => cmpr_deg:auto_generated.datab[8]
datab[9] => cmpr_deg:auto_generated.datab[9]
datab[10] => cmpr_deg:auto_generated.datab[10]
datab[11] => cmpr_deg:auto_generated.datab[11]
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
alb <= <GND>
aeb <= <GND>
agb <= <GND>
aleb <= <GND>
aneb <= <GND>
ageb <= cmpr_deg:auto_generated.ageb


|5050PWM|pwm:inst8|lpm_compare1:inst18|lpm_compare:lpm_compare_component|cmpr_deg:auto_generated
dataa[0] => op_1.IN24
dataa[1] => op_1.IN22
dataa[2] => op_1.IN20
dataa[3] => op_1.IN18
dataa[4] => op_1.IN16
dataa[5] => op_1.IN14
dataa[6] => op_1.IN12
dataa[7] => op_1.IN10
dataa[8] => op_1.IN8
dataa[9] => op_1.IN6
dataa[10] => op_1.IN4
dataa[11] => op_1.IN2
datab[0] => op_1.IN23
datab[1] => op_1.IN21
datab[2] => op_1.IN19
datab[3] => op_1.IN17
datab[4] => op_1.IN15
datab[5] => op_1.IN13
datab[6] => op_1.IN11
datab[7] => op_1.IN9
datab[8] => op_1.IN7
datab[9] => op_1.IN5
datab[10] => op_1.IN3
datab[11] => op_1.IN1


|5050PWM|pwm:inst8|lpm_counter0:inst11
clock => lpm_counter:lpm_counter_component.clock
cout <= lpm_counter:lpm_counter_component.cout
q[0] <= lpm_counter:lpm_counter_component.q[0]
q[1] <= lpm_counter:lpm_counter_component.q[1]
q[2] <= lpm_counter:lpm_counter_component.q[2]
q[3] <= lpm_counter:lpm_counter_component.q[3]
q[4] <= lpm_counter:lpm_counter_component.q[4]
q[5] <= lpm_counter:lpm_counter_component.q[5]
q[6] <= lpm_counter:lpm_counter_component.q[6]
q[7] <= lpm_counter:lpm_counter_component.q[7]
q[8] <= lpm_counter:lpm_counter_component.q[8]
q[9] <= lpm_counter:lpm_counter_component.q[9]
q[10] <= lpm_counter:lpm_counter_component.q[10]
q[11] <= lpm_counter:lpm_counter_component.q[11]


|5050PWM|pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component
clock => cntr_gth:auto_generated.clock
clk_en => ~NO_FANOUT~
cnt_en => ~NO_FANOUT~
updown => ~NO_FANOUT~
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
data[5] => ~NO_FANOUT~
data[6] => ~NO_FANOUT~
data[7] => ~NO_FANOUT~
data[8] => ~NO_FANOUT~
data[9] => ~NO_FANOUT~
data[10] => ~NO_FANOUT~
data[11] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_gth:auto_generated.q[0]
q[1] <= cntr_gth:auto_generated.q[1]
q[2] <= cntr_gth:auto_generated.q[2]
q[3] <= cntr_gth:auto_generated.q[3]
q[4] <= cntr_gth:auto_generated.q[4]
q[5] <= cntr_gth:auto_generated.q[5]
q[6] <= cntr_gth:auto_generated.q[6]
q[7] <= cntr_gth:auto_generated.q[7]
q[8] <= cntr_gth:auto_generated.q[8]
q[9] <= cntr_gth:auto_generated.q[9]
q[10] <= cntr_gth:auto_generated.q[10]
q[11] <= cntr_gth:auto_generated.q[11]
cout <= cntr_gth:auto_generated.cout
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|5050PWM|pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
clock => counter_cella7.CLK
clock => counter_cella8.CLK
clock => counter_cella9.CLK
clock => counter_cella10.CLK
clock => counter_cella11.CLK
cout <= cout_bit.COMBOUT
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
q[5] <= counter_cella5.REGOUT
q[6] <= counter_cella6.REGOUT
q[7] <= counter_cella7.REGOUT
q[8] <= counter_cella8.REGOUT
q[9] <= counter_cella9.REGOUT
q[10] <= counter_cella10.REGOUT
q[11] <= counter_cella11.REGOUT


|5050PWM|pwm:inst8|74377b:inst6
Q4 <= enadff:15.Q
EN => 6.IN0
D4 => enadff:15.D
CLK => enadff:15.CLK
CLK => enadff:10.CLK
CLK => enadff:3.CLK
CLK => enadff:2.CLK
CLK => enadff:18.CLK
CLK => enadff:19.CLK
CLK => enadff:24.CLK
CLK => enadff:25.CLK
Q3 <= enadff:10.Q
D3 => enadff:10.D
Q2 <= enadff:3.Q
D2 => enadff:3.D
Q1 <= enadff:2.Q
D1 => enadff:2.D
Q5 <= enadff:18.Q
D5 => enadff:18.D
Q6 <= enadff:19.Q
D6 => enadff:19.D
Q7 <= enadff:24.Q
D7 => enadff:24.D
Q8 <= enadff:25.Q
D8 => enadff:25.D


|5050PWM|pwm:inst8|74377b:inst6|enadff:15
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst8|74377b:inst6|enadff:10
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst8|74377b:inst6|enadff:3
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst8|74377b:inst6|enadff:2
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst8|74377b:inst6|enadff:18
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst8|74377b:inst6|enadff:19
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst8|74377b:inst6|enadff:24
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst8|74377b:inst6|enadff:25
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst8|74377b:inst7
Q4 <= enadff:15.Q
EN => 6.IN0
D4 => enadff:15.D
CLK => enadff:15.CLK
CLK => enadff:10.CLK
CLK => enadff:3.CLK
CLK => enadff:2.CLK
CLK => enadff:18.CLK
CLK => enadff:19.CLK
CLK => enadff:24.CLK
CLK => enadff:25.CLK
Q3 <= enadff:10.Q
D3 => enadff:10.D
Q2 <= enadff:3.Q
D2 => enadff:3.D
Q1 <= enadff:2.Q
D1 => enadff:2.D
Q5 <= enadff:18.Q
D5 => enadff:18.D
Q6 <= enadff:19.Q
D6 => enadff:19.D
Q7 <= enadff:24.Q
D7 => enadff:24.D
Q8 <= enadff:25.Q
D8 => enadff:25.D


|5050PWM|pwm:inst8|74377b:inst7|enadff:15
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst8|74377b:inst7|enadff:10
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst8|74377b:inst7|enadff:3
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst8|74377b:inst7|enadff:2
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst8|74377b:inst7|enadff:18
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst8|74377b:inst7|enadff:19
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst8|74377b:inst7|enadff:24
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA


|5050PWM|pwm:inst8|74377b:inst7|enadff:25
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
PRN => 3.PRESET
CLRN => 3.ACLR
D => 3.DATAIN
CLK => 3.CLK
ENA => 3.ENA