📄 5050pwm.tan.qmsg
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{ "Info" "ITDB_FULL_SLACK_RESULT" "clock register CLOCK_MY:inst5\|SENSOR_AB\[1\] register CLOCK_MY:inst5\|COUNTER\[31\] 33.989 ns " "Info: Slack time is 33.989 ns for clock \"clock\" between source register \"CLOCK_MY:inst5\|SENSOR_AB\[1\]\" and destination register \"CLOCK_MY:inst5\|COUNTER\[31\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "166.36 MHz 6.011 ns " "Info: Fmax is 166.36 MHz (period= 6.011 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "39.739 ns + Largest register register " "Info: + Largest register to register requirement is 39.739 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "40.000 ns + " "Info: + Setup relationship between source and destination is 40.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 40.000 ns " "Info: + Latch edge is 40.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clock 40.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"clock\" is 40.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clock 40.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"clock\" is 40.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.911 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.911 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_153 109 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 109; CLK Node = 'clock'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 520 -48 120 536 "clock" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.731 ns) + CELL(0.711 ns) 2.911 ns CLOCK_MY:inst5\|COUNTER\[31\] 2 REG LC_X23_Y5_N5 3 " "Info: 2: + IC(0.731 ns) + CELL(0.711 ns) = 2.911 ns; Loc. = LC_X23_Y5_N5; Fanout = 3; REG Node = 'CLOCK_MY:inst5\|COUNTER\[31\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.442 ns" { clock CLOCK_MY:inst5|COUNTER[31] } "NODE_NAME" } } { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 107 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.89 % ) " "Info: Total cell delay = 2.180 ns ( 74.89 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.731 ns ( 25.11 % ) " "Info: Total interconnect delay = 0.731 ns ( 25.11 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.911 ns" { clock CLOCK_MY:inst5|COUNTER[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.911 ns" { clock clock~out0 CLOCK_MY:inst5|COUNTER[31] } { 0.000ns 0.000ns 0.731ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.911 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 2.911 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_153 109 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 109; CLK Node = 'clock'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 520 -48 120 536 "clock" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.731 ns) + CELL(0.711 ns) 2.911 ns CLOCK_MY:inst5\|SENSOR_AB\[1\] 2 REG LC_X24_Y5_N4 4 " "Info: 2: + IC(0.731 ns) + CELL(0.711 ns) = 2.911 ns; Loc. = LC_X24_Y5_N4; Fanout = 4; REG Node = 'CLOCK_MY:inst5\|SENSOR_AB\[1\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.442 ns" { clock CLOCK_MY:inst5|SENSOR_AB[1] } "NODE_NAME" } } { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 107 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.89 % ) " "Info: Total cell delay = 2.180 ns ( 74.89 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.731 ns ( 25.11 % ) " "Info: Total interconnect delay = 0.731 ns ( 25.11 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.911 ns" { clock CLOCK_MY:inst5|SENSOR_AB[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.911 ns" { clock clock~out0 CLOCK_MY:inst5|SENSOR_AB[1] } { 0.000ns 0.000ns 0.731ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.911 ns" { clock CLOCK_MY:inst5|COUNTER[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.911 ns" { clock clock~out0 CLOCK_MY:inst5|COUNTER[31] } { 0.000ns 0.000ns 0.731ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.911 ns" { clock CLOCK_MY:inst5|SENSOR_AB[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.911 ns" { clock clock~out0 CLOCK_MY:inst5|SENSOR_AB[1] } { 0.000ns 0.000ns 0.731ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 107 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" { } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 107 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.911 ns" { clock CLOCK_MY:inst5|COUNTER[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.911 ns" { clock clock~out0 CLOCK_MY:inst5|COUNTER[31] } { 0.000ns 0.000ns 0.731ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.911 ns" { clock CLOCK_MY:inst5|SENSOR_AB[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.911 ns" { clock clock~out0 CLOCK_MY:inst5|SENSOR_AB[1] } { 0.000ns 0.000ns 0.731ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.750 ns - Longest register register " "Info: - Longest register to register delay is 5.750 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CLOCK_MY:inst5\|SENSOR_AB\[1\] 1 REG LC_X24_Y5_N4 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y5_N4; Fanout = 4; REG Node = 'CLOCK_MY:inst5\|SENSOR_AB\[1\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK_MY:inst5|SENSOR_AB[1] } "NODE_NAME" } } { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 107 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.291 ns) + CELL(0.590 ns) 1.881 ns CLOCK_MY:inst5\|Add1~874 2 COMB LC_X23_Y8_N2 85 " "Info: 2: + IC(1.291 ns) + CELL(0.590 ns) = 1.881 ns; Loc. = LC_X23_Y8_N2; Fanout = 85; COMB Node = 'CLOCK_MY:inst5\|Add1~874'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.881 ns" { CLOCK_MY:inst5|SENSOR_AB[1] CLOCK_MY:inst5|Add1~874 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.366 ns) + CELL(0.564 ns) 3.811 ns CLOCK_MY:inst5\|COUNTER\[6\]~1511 3 COMB LC_X23_Y7_N0 2 " "Info: 3: + IC(1.366 ns) + CELL(0.564 ns) = 3.811 ns; Loc. = LC_X23_Y7_N0; Fanout = 2; COMB Node = 'CLOCK_MY:inst5\|COUNTER\[6\]~1511'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.930 ns" { CLOCK_MY:inst5|Add1~874 CLOCK_MY:inst5|COUNTER[6]~1511 } "NODE_NAME" } } { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 107 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 3.889 ns CLOCK_MY:inst5\|COUNTER\[7\]~1507 4 COMB LC_X23_Y7_N1 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 3.889 ns; Loc. = LC_X23_Y7_N1; Fanout = 2; COMB Node = 'CLOCK_MY:inst5\|COUNTER\[7\]~1507'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { CLOCK_MY:inst5|COUNTER[6]~1511 CLOCK_MY:inst5|COUNTER[7]~1507 } "NODE_NAME" } } { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 107 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 3.967 ns CLOCK_MY:inst5\|COUNTER\[8\]~1538 5 COMB LC_X23_Y7_N2 2 " "Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 3.967 ns; Loc. = LC_X23_Y7_N2; Fanout = 2; COMB Node = 'CLOCK_MY:inst5\|COUNTER\[8\]~1538'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { CLOCK_MY:inst5|COUNTER[7]~1507 CLOCK_MY:inst5|COUNTER[8]~1538 } "NODE_NAME" } } { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 107 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 4.045 ns CLOCK_MY:inst5\|COUNTER\[9\]~1534 6 COMB LC_X23_Y7_N3 2 " "Info: 6: + IC(0.000 ns) + CELL(0.078 ns) = 4.045 ns; Loc. = LC_X23_Y7_N3; Fanout = 2; COMB Node = 'CLOCK_MY:inst5\|COUNTER\[9\]~1534'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { CLOCK_MY:inst5|COUNTER[8]~1538 CLOCK_MY:inst5|COUNTER[9]~1534 } "NODE_NAME" } } { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 107 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 4.223 ns CLOCK_MY:inst5\|COUNTER\[10\]~1530 7 COMB LC_X23_Y7_N4 6 " "Info: 7: + IC(0.000 ns) + CELL(0.178 ns) = 4.223 ns; Loc. = LC_X23_Y7_N4; Fanout = 6; COMB Node = 'CLOCK_MY:inst5\|COUNTER\[10\]~1530'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.178 ns" { CLOCK_MY:inst5|COUNTER[9]~1534 CLOCK_MY:inst5|COUNTER[10]~1530 } "NODE_NAME" } } { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 107 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 4.431 ns CLOCK_MY:inst5\|COUNTER\[15\]~1510 8 COMB LC_X23_Y7_N9 6 " "Info: 8: + IC(0.000 ns) + CELL(0.208 ns) = 4.431 ns; Loc. = LC_X23_Y7_N9; Fanout = 6; COMB Node = 'CLOCK_MY:inst5\|COUNTER\[15\]~1510'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.208 ns" { CLOCK_MY:inst5|COUNTER[10]~1530 CLOCK_MY:inst5|COUNTER[15]~1510 } "NODE_NAME" } } { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 107 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 4.567 ns CLOCK_MY:inst5\|COUNTER\[20\]~1520 9 COMB LC_X23_Y6_N4 6 " "Info: 9: + IC(0.000 ns) + CELL(0.136 ns) = 4.567 ns; Loc. = LC_X23_Y6_N4; Fanout = 6; COMB Node = 'CLOCK_MY:inst5\|COUNTER\[20\]~1520'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { CLOCK_MY:inst5|COUNTER[15]~1510 CLOCK_MY:inst5|COUNTER[20]~1520 } "NODE_NAME" } } { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 107 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 4.775 ns CLOCK_MY:inst5\|COUNTER\[25\]~1532 10 COMB LC_X23_Y6_N9 6 " "Info: 10: + IC(0.000 ns) + CELL(0.208 ns) = 4.775 ns; Loc. = LC_X23_Y6_N9; Fanout = 6; COMB Node = 'CLOCK_MY:inst5\|COUNTER\[25\]~1532'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.208 ns" { CLOCK_MY:inst5|COUNTER[20]~1520 CLOCK_MY:inst5|COUNTER[25]~1532 } "NODE_NAME" } } { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 107 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 4.911 ns CLOCK_MY:inst5\|COUNTER\[30\]~1513 11 COMB LC_X23_Y5_N4 1 " "Info: 11: + IC(0.000 ns) + CELL(0.136 ns) = 4.911 ns; Loc. = LC_X23_Y5_N4; Fanout = 1; COMB Node = 'CLOCK_MY:inst5\|COUNTER\[30\]~1513'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { CLOCK_MY:inst5|COUNTER[25]~1532 CLOCK_MY:inst5|COUNTER[30]~1513 } "NODE_NAME" } } { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 107 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 5.750 ns CLOCK_MY:inst5\|COUNTER\[31\] 12 REG LC_X23_Y5_N5 3 " "Info: 12: + IC(0.000 ns) + CELL(0.839 ns) = 5.750 ns; Loc. = LC_X23_Y5_N5; Fanout = 3; REG Node = 'CLOCK_MY:inst5\|COUNTER\[31\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.839 ns" { CLOCK_MY:inst5|COUNTER[30]~1513 CLOCK_MY:inst5|COUNTER[31] } "NODE_NAME" } } { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 107 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.093 ns ( 53.79 % ) " "Info: Total cell delay = 3.093 ns ( 53.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.657 ns ( 46.21 % ) " "Info: Total interconnect delay = 2.657 ns ( 46.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.750 ns" { CLOCK_MY:inst5|SENSOR_AB[1] CLOCK_MY:inst5|Add1~874 CLOCK_MY:inst5|COUNTER[6]~1511 CLOCK_MY:inst5|COUNTER[7]~1507 CLOCK_MY:inst5|COUNTER[8]~1538 CLOCK_MY:inst5|COUNTER[9]~1534 CLOCK_MY:inst5|COUNTER[10]~1530 CLOCK_MY:inst5|COUNTER[15]~1510 CLOCK_MY:inst5|COUNTER[20]~1520 CLOCK_MY:inst5|COUNTER[25]~1532 CLOCK_MY:inst5|COUNTER[30]~1513 CLOCK_MY:inst5|COUNTER[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.750 ns" { CLOCK_MY:inst5|SENSOR_AB[1] CLOCK_MY:inst5|Add1~874 CLOCK_MY:inst5|COUNTER[6]~1511 CLOCK_MY:inst5|COUNTER[7]~1507 CLOCK_MY:inst5|COUNTER[8]~1538 CLOCK_MY:inst5|COUNTER[9]~1534 CLOCK_MY:inst5|COUNTER[10]~1530 CLOCK_MY:inst5|COUNTER[15]~1510 CLOCK_MY:inst5|COUNTER[20]~1520 CLOCK_MY:inst5|COUNTER[25]~1532 CLOCK_MY:inst5|COUNTER[30]~1513 CLOCK_MY:inst5|COUNTER[31] } { 0.000ns 1.291ns 1.366ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.590ns 0.564ns 0.078ns 0.078ns 0.078ns 0.178ns 0.208ns 0.136ns 0.208ns 0.136ns 0.839ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.911 ns" { clock CLOCK_MY:inst5|COUNTER[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.911 ns" { clock clock~out0 CLOCK_MY:inst5|COUNTER[31] } { 0.000ns 0.000ns 0.731ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.911 ns" { clock CLOCK_MY:inst5|SENSOR_AB[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.911 ns" { clock clock~out0 CLOCK_MY:inst5|SENSOR_AB[1] } { 0.000ns 0.000ns 0.731ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.750 ns" { CLOCK_MY:inst5|SENSOR_AB[1] CLOCK_MY:inst5|Add1~874 CLOCK_MY:inst5|COUNTER[6]~1511 CLOCK_MY:inst5|COUNTER[7]~1507 CLOCK_MY:inst5|COUNTER[8]~1538 CLOCK_MY:inst5|COUNTER[9]~1534 CLOCK_MY:inst5|COUNTER[10]~1530 CLOCK_MY:inst5|COUNTER[15]~1510 CLOCK_MY:inst5|COUNTER[20]~1520 CLOCK_MY:inst5|COUNTER[25]~1532 CLOCK_MY:inst5|COUNTER[30]~1513 CLOCK_MY:inst5|COUNTER[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.750 ns" { CLOCK_MY:inst5|SENSOR_AB[1] CLOCK_MY:inst5|Add1~874 CLOCK_MY:inst5|COUNTER[6]~1511 CLOCK_MY:inst5|COUNTER[7]~1507 CLOCK_MY:inst5|COUNTER[8]~1538 CLOCK_MY:inst5|COUNTER[9]~1534 CLOCK_MY:inst5|COUNTER[10]~1530 CLOCK_MY:inst5|COUNTER[15]~1510 CLOCK_MY:inst5|COUNTER[20]~1520 CLOCK_MY:inst5|COUNTER[25]~1532 CLOCK_MY:inst5|COUNTER[30]~1513 CLOCK_MY:inst5|COUNTER[31] } { 0.000ns 1.291ns 1.366ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.590ns 0.564ns 0.078ns 0.078ns 0.078ns 0.178ns 0.208ns 0.136ns 0.208ns 0.136ns 0.839ns } } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "myPLL:inst2\|altpll:altpll_component\|_clk0 register pwm:inst8\|lpm_counter0:inst11\|lpm_counter:lpm_counter_component\|cntr_gth:auto_generated\|safe_q\[11\] register pwm:inst8\|lpm_counter0:inst11\|lpm_counter:lpm_counter_component\|cntr_gth:auto_generated\|safe_q\[11\] 1.045 ns " "Info: Minimum slack time is 1.045 ns for clock \"myPLL:inst2\|altpll:altpll_component\|_clk0\" between source register \"pwm:inst8\|lpm_counter0:inst11\|lpm_counter:lpm_counter_component\|cntr_gth:auto_generated\|safe_q\[11\]\" and destination register \"pwm:inst8\|lpm_counter0:inst11\|lpm_counter:lpm_counter_component\|cntr_gth:auto_generated\|safe_q\[11\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.836 ns + Shortest register register " "Info: + Shortest register to register delay is 0.836 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pwm:inst8\|lpm_counter0:inst11\|lpm_counter:lpm_counter_component\|cntr_gth:auto_generated\|safe_q\[11\] 1 REG LC_X24_Y3_N5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y3_N5; Fanout = 3; REG Node = 'pwm:inst8\|lpm_counter0:inst11\|lpm_counter:lpm_counter_component\|cntr_gth:auto_generated\|safe_q\[11\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] } "NODE_NAME" } } { "db/cntr_gth.tdf" "" { Text "D:/FPGA/5050PWM_V54/db/cntr_gth.tdf" 139 8 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.527 ns) + CELL(0.309 ns) 0.836 ns pwm:inst8\|lpm_counter0:inst11\|lpm_counter:lpm_counter_component\|cntr_gth:auto_generated\|safe_q\[11\] 2 REG LC_X24_Y3_N5 3 " "Info: 2: + IC(0.527 ns) + CELL(0.309 ns) = 0.836 ns; Loc. = LC_X24_Y3_N5; Fanout = 3; REG Node = 'pwm:inst8\|lpm_counter0:inst11\|lpm_counter:lpm_counter_component\|cntr_gth:auto_generated\|safe_q\[11\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.836 ns" { pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] } "NODE_NAME" } } { "db/cntr_gth.tdf" "" { Text "D:/FPGA/5050PWM_V54/db/cntr_gth.tdf" 139 8 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 36.96 % ) " "Info: Total cell delay = 0.309 ns ( 36.96 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.527 ns ( 63.04 % ) " "Info: Total interconnect delay = 0.527 ns ( 63.04 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.836 ns" { pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.836 ns" { pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] } { 0.000ns 0.527ns } { 0.000ns 0.309ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -1.885 ns " "Info: + Latch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination myPLL:inst2\|altpll:altpll_component\|_clk0 10.000 ns -1.885 ns 50 " "Info: Clock period of Destination clock \"myPLL:inst2\|altpll:altpll_component\|_clk0\" is 10.000 ns with offset of -1.885 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.885 ns " "Info: - Launch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source myPLL:inst2\|altpll:altpll_component\|_clk0 10.000 ns -1.885 ns 50 " "Info: Clock period of Source clock \"myPLL:inst2\|altpll:altpll_component\|_clk0\" is 10.000 ns with offset of -1.885 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "myPLL:inst2\|altpll:altpll_component\|_clk0 destination 2.352 ns + Longest register " "Info: + Longest clock path from clock \"myPLL:inst2\|altpll:altpll_component\|_clk0\" to destination register is 2.352 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns myPLL:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_2 39 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 39; CLK Node = 'myPLL:inst2\|altpll:altpll_component\|_clk0'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { myPLL:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.641 ns) + CELL(0.711 ns) 2.352 ns pwm:inst8\|lpm_counter0:inst11\|lpm_counter:lpm_counter_component\|cntr_gth:auto_generated\|safe_q\[11\] 2 REG LC_X24_Y3_N5 3 " "Info: 2: + IC(1.641 ns) + CELL(0.711 ns) = 2.352 ns; Loc. = LC_X24_Y3_N5; Fanout = 3; REG Node = 'pwm:inst8\|lpm_counter0:inst11\|lpm_counter:lpm_counter_component\|cntr_gth:auto_generated\|safe_q\[11\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.352 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] } "NODE_NAME" } } { "db/cntr_gth.tdf" "" { Text "D:/FPGA/5050PWM_V54/db/cntr_gth.tdf" 139 8 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 30.23 % ) " "Info: Total cell delay = 0.711 ns ( 30.23 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.641 ns ( 69.77 % ) " "Info: Total interconnect delay = 1.641 ns ( 69.77 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.352 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.352 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] } { 0.000ns 1.641ns } { 0.000ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "myPLL:inst2\|altpll:altpll_component\|_clk0 source 2.352 ns - Shortest register " "Info: - Shortest clock path from clock \"myPLL:inst2\|altpll:altpll_component\|_clk0\" to source register is 2.352 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns myPLL:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_2 39 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 39; CLK Node = 'myPLL:inst2\|altpll:altpll_component\|_clk0'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { myPLL:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.641 ns) + CELL(0.711 ns) 2.352 ns pwm:inst8\|lpm_counter0:inst11\|lpm_counter:lpm_counter_component\|cntr_gth:auto_generated\|safe_q\[11\] 2 REG LC_X24_Y3_N5 3 " "Info: 2: + IC(1.641 ns) + CELL(0.711 ns) = 2.352 ns; Loc. = LC_X24_Y3_N5; Fanout = 3; REG Node = 'pwm:inst8\|lpm_counter0:inst11\|lpm_counter:lpm_counter_component\|cntr_gth:auto_generated\|safe_q\[11\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.352 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] } "NODE_NAME" } } { "db/cntr_gth.tdf" "" { Text "D:/FPGA/5050PWM_V54/db/cntr_gth.tdf" 139 8 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 30.23 % ) " "Info: Total cell delay = 0.711 ns ( 30.23 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.641 ns ( 69.77 % ) " "Info: Total interconnect delay = 1.641 ns ( 69.77 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.352 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.352 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] } { 0.000ns 1.641ns } { 0.000ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.352 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.352 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] } { 0.000ns 1.641ns } { 0.000ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.352 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.352 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] } { 0.000ns 1.641ns } { 0.000ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "db/cntr_gth.tdf" "" { Text "D:/FPGA/5050PWM_V54/db/cntr_gth.tdf" 139 8 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" { } { { "db/cntr_gth.tdf" "" { Text "D:/FPGA/5050PWM_V54/db/cntr_gth.tdf" 139 8 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.352 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.352 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] } { 0.000ns 1.641ns } { 0.000ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.352 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.352 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] } { 0.000ns 1.641ns } { 0.000ns 0.711ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.836 ns" { pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.836 ns" { pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] } { 0.000ns 0.527ns } { 0.000ns 0.309ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.352 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.352 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] } { 0.000ns 1.641ns } { 0.000ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.352 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.352 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] } { 0.000ns 1.641ns } { 0.000ns 0.711ns } } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clock register CLOCK_MY:inst5\|COUNTER\[31\] register CLOCK_MY:inst5\|COUNTER\[31\] 1.031 ns " "Info: Minimum slack time is 1.031 ns for clock \"clock\" between source register \"CLOCK_MY:inst5\|COUNTER\[31\]\" and destination register \"CLOCK_MY:inst5\|COUNTER\[31\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.822 ns + Shortest register register " "Info: + Shortest register to register delay is 0.822 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CLOCK_MY:inst5\|COUNTER\[31\] 1 REG LC_X23_Y5_N5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y5_N5; Fanout = 3; REG Node = 'CLOCK_MY:inst5\|COUNTER\[31\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK_MY:inst5|COUNTER[31] } "NODE_NAME" } } { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 107 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.513 ns) + CELL(0.309 ns) 0.822 ns CLOCK_MY:inst5\|COUNTER\[31\] 2 REG LC_X23_Y5_N5 3 " "Info: 2: + IC(0.513 ns) + CELL(0.309 ns) = 0.822 ns; Loc. = LC_X23_Y5_N5; Fanout = 3; REG Node = 'CLOCK_MY:inst5\|COUNTER\[31\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c⌨️ 快捷键说明
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