5050pwm.tan.qmsg

FPGA 实现基于ISA接口的3路编码器计数

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "CLOCK_MY:inst5\|comb~2049 " "Info: Detected gated clock \"CLOCK_MY:inst5\|comb~2049\" as buffer" {  } { { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLOCK_MY:inst5\|comb~2049" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "CLOCK_MY:inst5\|comb~2050 " "Info: Detected gated clock \"CLOCK_MY:inst5\|comb~2050\" as buffer" {  } { { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLOCK_MY:inst5\|comb~2050" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "myPLL:inst2\|altpll:altpll_component\|_clk0 register pwm:inst7\|lpm_counter0:inst11\|lpm_counter:lpm_counter_component\|cntr_gth:auto_generated\|safe_q\[6\] register pwm:inst7\|lpm_dff0:inst\|lpm_ff:lpm_ff_component\|dffs\[0\] 5.332 ns " "Info: Slack time is 5.332 ns for clock \"myPLL:inst2\|altpll:altpll_component\|_clk0\" between source register \"pwm:inst7\|lpm_counter0:inst11\|lpm_counter:lpm_counter_component\|cntr_gth:auto_generated\|safe_q\[6\]\" and destination register \"pwm:inst7\|lpm_dff0:inst\|lpm_ff:lpm_ff_component\|dffs\[0\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "214.22 MHz 4.668 ns " "Info: Fmax is 214.22 MHz (period= 4.668 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "9.739 ns + Largest register register " "Info: + Largest register to register requirement is 9.739 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "10.000 ns + " "Info: + Setup relationship between source and destination is 10.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 8.115 ns " "Info: + Latch edge is 8.115 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination myPLL:inst2\|altpll:altpll_component\|_clk0 10.000 ns -1.885 ns  50 " "Info: Clock period of Destination clock \"myPLL:inst2\|altpll:altpll_component\|_clk0\" is 10.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.885 ns " "Info: - Launch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source myPLL:inst2\|altpll:altpll_component\|_clk0 10.000 ns -1.885 ns  50 " "Info: Clock period of Source clock \"myPLL:inst2\|altpll:altpll_component\|_clk0\" is 10.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "myPLL:inst2\|altpll:altpll_component\|_clk0 destination 2.385 ns + Shortest register " "Info: + Shortest clock path from clock \"myPLL:inst2\|altpll:altpll_component\|_clk0\" to destination register is 2.385 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns myPLL:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_2 39 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 39; CLK Node = 'myPLL:inst2\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { myPLL:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.674 ns) + CELL(0.711 ns) 2.385 ns pwm:inst7\|lpm_dff0:inst\|lpm_ff:lpm_ff_component\|dffs\[0\] 2 REG LC_X23_Y11_N6 1 " "Info: 2: + IC(1.674 ns) + CELL(0.711 ns) = 2.385 ns; Loc. = LC_X23_Y11_N6; Fanout = 1; REG Node = 'pwm:inst7\|lpm_dff0:inst\|lpm_ff:lpm_ff_component\|dffs\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.385 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst7|lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } } { "lpm_ff.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_ff.tdf" 60 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 29.81 % ) " "Info: Total cell delay = 0.711 ns ( 29.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.674 ns ( 70.19 % ) " "Info: Total interconnect delay = 1.674 ns ( 70.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.385 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst7|lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.385 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst7|lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[0] } { 0.000ns 1.674ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "myPLL:inst2\|altpll:altpll_component\|_clk0 source 2.385 ns - Longest register " "Info: - Longest clock path from clock \"myPLL:inst2\|altpll:altpll_component\|_clk0\" to source register is 2.385 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns myPLL:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_2 39 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 39; CLK Node = 'myPLL:inst2\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { myPLL:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.674 ns) + CELL(0.711 ns) 2.385 ns pwm:inst7\|lpm_counter0:inst11\|lpm_counter:lpm_counter_component\|cntr_gth:auto_generated\|safe_q\[6\] 2 REG LC_X22_Y11_N0 6 " "Info: 2: + IC(1.674 ns) + CELL(0.711 ns) = 2.385 ns; Loc. = LC_X22_Y11_N0; Fanout = 6; REG Node = 'pwm:inst7\|lpm_counter0:inst11\|lpm_counter:lpm_counter_component\|cntr_gth:auto_generated\|safe_q\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.385 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst7|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[6] } "NODE_NAME" } } { "db/cntr_gth.tdf" "" { Text "D:/FPGA/5050PWM_V54/db/cntr_gth.tdf" 139 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 29.81 % ) " "Info: Total cell delay = 0.711 ns ( 29.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.674 ns ( 70.19 % ) " "Info: Total interconnect delay = 1.674 ns ( 70.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.385 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst7|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.385 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst7|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[6] } { 0.000ns 1.674ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.385 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst7|lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.385 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst7|lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[0] } { 0.000ns 1.674ns } { 0.000ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.385 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst7|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.385 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst7|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[6] } { 0.000ns 1.674ns } { 0.000ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "db/cntr_gth.tdf" "" { Text "D:/FPGA/5050PWM_V54/db/cntr_gth.tdf" 139 8 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "lpm_ff.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_ff.tdf" 60 7 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.385 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst7|lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.385 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst7|lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[0] } { 0.000ns 1.674ns } { 0.000ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.385 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst7|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.385 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst7|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[6] } { 0.000ns 1.674ns } { 0.000ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.407 ns - Longest register register " "Info: - Longest register to register delay is 4.407 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pwm:inst7\|lpm_counter0:inst11\|lpm_counter:lpm_counter_component\|cntr_gth:auto_generated\|safe_q\[6\] 1 REG LC_X22_Y11_N0 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y11_N0; Fanout = 6; REG Node = 'pwm:inst7\|lpm_counter0:inst11\|lpm_counter:lpm_counter_component\|cntr_gth:auto_generated\|safe_q\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pwm:inst7|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[6] } "NODE_NAME" } } { "db/cntr_gth.tdf" "" { Text "D:/FPGA/5050PWM_V54/db/cntr_gth.tdf" 139 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.172 ns) + CELL(0.590 ns) 1.762 ns pwm:inst7\|lpm_compare1:inst18\|lpm_compare:lpm_compare_component\|cmpr_deg:auto_generated\|aeb_int~70 2 COMB LC_X23_Y11_N9 1 " "Info: 2: + IC(1.172 ns) + CELL(0.590 ns) = 1.762 ns; Loc. = LC_X23_Y11_N9; Fanout = 1; COMB Node = 'pwm:inst7\|lpm_compare1:inst18\|lpm_compare:lpm_compare_component\|cmpr_deg:auto_generated\|aeb_int~70'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.762 ns" { pwm:inst7|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[6] pwm:inst7|lpm_compare1:inst18|lpm_compare:lpm_compare_component|cmpr_deg:auto_generated|aeb_int~70 } "NODE_NAME" } } { "db/cmpr_deg.tdf" "" { Text "D:/FPGA/5050PWM_V54/db/cmpr_deg.tdf" 29 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.134 ns) + CELL(0.590 ns) 3.486 ns pwm:inst7\|lpm_compare1:inst18\|lpm_compare:lpm_compare_component\|cmpr_deg:auto_generated\|aeb_int~74 3 COMB LC_X23_Y11_N8 1 " "Info: 3: + IC(1.134 ns) + CELL(0.590 ns) = 3.486 ns; Loc. = LC_X23_Y11_N8; Fanout = 1; COMB Node = 'pwm:inst7\|lpm_compare1:inst18\|lpm_compare:lpm_compare_component\|cmpr_deg:auto_generated\|aeb_int~74'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.724 ns" { pwm:inst7|lpm_compare1:inst18|lpm_compare:lpm_compare_component|cmpr_deg:auto_generated|aeb_int~70 pwm:inst7|lpm_compare1:inst18|lpm_compare:lpm_compare_component|cmpr_deg:auto_generated|aeb_int~74 } "NODE_NAME" } } { "db/cmpr_deg.tdf" "" { Text "D:/FPGA/5050PWM_V54/db/cmpr_deg.tdf" 29 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.478 ns) 4.407 ns pwm:inst7\|lpm_dff0:inst\|lpm_ff:lpm_ff_component\|dffs\[0\] 4 REG LC_X23_Y11_N6 1 " "Info: 4: + IC(0.443 ns) + CELL(0.478 ns) = 4.407 ns; Loc. = LC_X23_Y11_N6; Fanout = 1; REG Node = 'pwm:inst7\|lpm_dff0:inst\|lpm_ff:lpm_ff_component\|dffs\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.921 ns" { pwm:inst7|lpm_compare1:inst18|lpm_compare:lpm_compare_component|cmpr_deg:auto_generated|aeb_int~74 pwm:inst7|lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } } { "lpm_ff.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_ff.tdf" 60 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.658 ns ( 37.62 % ) " "Info: Total cell delay = 1.658 ns ( 37.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.749 ns ( 62.38 % ) " "Info: Total interconnect delay = 2.749 ns ( 62.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.407 ns" { pwm:inst7|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[6] pwm:inst7|lpm_compare1:inst18|lpm_compare:lpm_compare_component|cmpr_deg:auto_generated|aeb_int~70 pwm:inst7|lpm_compare1:inst18|lpm_compare:lpm_compare_component|cmpr_deg:auto_generated|aeb_int~74 pwm:inst7|lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.407 ns" { pwm:inst7|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[6] pwm:inst7|lpm_compare1:inst18|lpm_compare:lpm_compare_component|cmpr_deg:auto_generated|aeb_int~70 pwm:inst7|lpm_compare1:inst18|lpm_compare:lpm_compare_component|cmpr_deg:auto_generated|aeb_int~74 pwm:inst7|lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[0] } { 0.000ns 1.172ns 1.134ns 0.443ns } { 0.000ns 0.590ns 0.590ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.385 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst7|lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.385 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst7|lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[0] } { 0.000ns 1.674ns } { 0.000ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.385 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst7|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.385 ns" { myPLL:inst2|altpll:altpll_component|_clk0 pwm:inst7|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[6] } { 0.000ns 1.674ns } { 0.000ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.407 ns" { pwm:inst7|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[6] pwm:inst7|lpm_compare1:inst18|lpm_compare:lpm_compare_component|cmpr_deg:auto_generated|aeb_int~70 pwm:inst7|lpm_compare1:inst18|lpm_compare:lpm_compare_component|cmpr_deg:auto_generated|aeb_int~74 pwm:inst7|lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.407 ns" { pwm:inst7|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[6] pwm:inst7|lpm_compare1:inst18|lpm_compare:lpm_compare_component|cmpr_deg:auto_generated|aeb_int~70 pwm:inst7|lpm_compare1:inst18|lpm_compare:lpm_compare_component|cmpr_deg:auto_generated|aeb_int~74 pwm:inst7|lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[0] } { 0.000ns 1.172ns 1.134ns 0.443ns } { 0.000ns 0.590ns 0.590ns 0.478ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}