5050pwm.tan.qmsg

FPGA 实现基于ISA接口的3路编码器计数

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "CLOCK_MY:inst5\|DATA_OUT\[0\]\$latch " "Warning: Node \"CLOCK_MY:inst5\|DATA_OUT\[0\]\$latch\" is a latch" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "CLOCK_MY:inst5\|comb_1011 " "Warning: Node \"CLOCK_MY:inst5\|comb_1011\" is a latch" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "CLOCK_MY:inst5\|DATA_OUT\[3\]\$latch " "Warning: Node \"CLOCK_MY:inst5\|DATA_OUT\[3\]\$latch\" is a latch" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "CLOCK_MY:inst5\|DATA_OUT\[6\]\$latch " "Warning: Node \"CLOCK_MY:inst5\|DATA_OUT\[6\]\$latch\" is a latch" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "CLOCK_MY:inst5\|DATA_OUT\[5\]\$latch " "Warning: Node \"CLOCK_MY:inst5\|DATA_OUT\[5\]\$latch\" is a latch" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "CLOCK_MY:inst5\|DATA_OUT\[1\]\$latch " "Warning: Node \"CLOCK_MY:inst5\|DATA_OUT\[1\]\$latch\" is a latch" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "CLOCK_MY:inst5\|DATA_OUT\[7\]\$latch " "Warning: Node \"CLOCK_MY:inst5\|DATA_OUT\[7\]\$latch\" is a latch" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "CLOCK_MY:inst5\|DATA_OUT\[4\]\$latch " "Warning: Node \"CLOCK_MY:inst5\|DATA_OUT\[4\]\$latch\" is a latch" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "CLOCK_MY:inst5\|DATA_OUT\[2\]\$latch " "Warning: Node \"CLOCK_MY:inst5\|DATA_OUT\[2\]\$latch\" is a latch" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" {  } {  } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "WR " "Info: Assuming node \"WR\" is an undefined clock" {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 400 -48 120 416 "WR" "" } { 392 120 224 408 "wr" "" } { 808 144 200 824 "wr" "" } { 384 584 632 400 "wr" "" } { 1064 272 360 1080 "WR" "" } { 560 792 840 576 "wr" "" } { 752 792 840 768 "wr" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "WR" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "addr\[0\] " "Info: Assuming node \"addr\[0\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 120 0 168 136 "addr\[9..4\]" "" } { 448 -48 120 464 "addr\[3..0\]" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "addr\[1\] " "Info: Assuming node \"addr\[1\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 120 0 168 136 "addr\[9..4\]" "" } { 448 -48 120 464 "addr\[3..0\]" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "RD " "Info: Assuming node \"RD\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 360 -48 120 376 "RD" "" } { 352 120 216 368 "RD" "" } { 1080 272 360 1096 "RD" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "addr\[2\] " "Info: Assuming node \"addr\[2\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 120 0 168 136 "addr\[9..4\]" "" } { 448 -48 120 464 "addr\[3..0\]" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "addr\[3\] " "Info: Assuming node \"addr\[3\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 120 0 168 136 "addr\[9..4\]" "" } { 448 -48 120 464 "addr\[3..0\]" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}