5050pwm.fit.summary

来自「FPGA 实现基于ISA接口的3路编码器计数」· SUMMARY 代码 · 共 13 行

Fitter Status : Successful - Mon Jul 07 15:30:13 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : 5050PWM
Top-level Entity Name : 5050PWM
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Final
Total logic elements : 434 / 5,980 ( 7 % )
Total pins : 40 / 185 ( 22 % )
Total virtual pins : 0
Total memory bits : 0 / 92,160 ( 0 % )
Total PLLs : 1 / 2 ( 50 % )