5050pwm.vho

FPGA 实现基于ISA接口的3路编码器计数

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 6.0 Build 178 04/27/2006 SJ Full Version"

-- DATE "07/07/2008 15:30:25"

-- 
-- Device: Altera EP1C6Q240C8 Package PQFP240
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	\5050PWM\ IS
    PORT (
	PWMout : OUT std_logic;
	WR : IN std_logic;
	addr : IN std_logic_vector(9 DOWNTO 0);
	clock : IN std_logic;
	D : INOUT std_logic_vector(7 DOWNTO 0);
	PHA0 : IN std_logic;
	PHB0 : IN std_logic;
	PHA1 : IN std_logic;
	PHB1 : IN std_logic;
	PHA2 : IN std_logic;
	PHB2 : IN std_logic;
	RD : IN std_logic;
	EN : OUT std_logic;
	addrSet : IN std_logic_vector(5 DOWNTO 0);
	AEN : IN std_logic;
	PWMen : OUT std_logic;
	LED2en : OUT std_logic;
	PWMout1 : OUT std_logic;
	PWMout0 : OUT std_logic
	);
END \5050PWM\;

ARCHITECTURE structure OF \5050PWM\ IS
SIGNAL GNDs : std_logic_vector(1024 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(1024 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL lcell_ff_enable_asynch_arcs_out : std_logic;
SIGNAL ww_PWMout : std_logic;
SIGNAL ww_WR : std_logic;
SIGNAL ww_addr : std_logic_vector(9 DOWNTO 0);
SIGNAL ww_clock : std_logic;
SIGNAL ww_PHA0 : std_logic;
SIGNAL ww_PHB0 : std_logic;
SIGNAL ww_PHA1 : std_logic;
SIGNAL ww_PHB1 : std_logic;
SIGNAL ww_PHA2 : std_logic;
SIGNAL ww_PHB2 : std_logic;
SIGNAL ww_RD : std_logic;
SIGNAL ww_EN : std_logic;
SIGNAL ww_addrSet : std_logic_vector(5 DOWNTO 0);
SIGNAL ww_AEN : std_logic;
SIGNAL ww_PWMen : std_logic;
SIGNAL ww_LED2en : std_logic;
SIGNAL ww_PWMout1 : std_logic;
SIGNAL ww_PWMout0 : std_logic;
SIGNAL \inst2|altpll_component|_clk0~I_INCLK_bus\ : std_logic_vector(1 DOWNTO 0);
SIGNAL \inst2|altpll_component|_clk0~I_CLK_bus\ : std_logic_vector(5 DOWNTO 0);
SIGNAL \D[7]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \D[6]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \D[5]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \D[4]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \D[3]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \D[2]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \D[1]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \D[0]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \clock~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \addr[2]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \addr[1]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \addr[3]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \addr[0]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \inst1|58~148_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst1|58~148_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst7|10|3~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst7|10|3~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst11|lpm_counter_component|auto_generated|safe_q[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst11|lpm_counter_component|auto_generated|safe_q[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst11|lpm_counter_component|auto_generated|safe_q[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst11|lpm_counter_component|auto_generated|safe_q[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst11|lpm_counter_component|auto_generated|safe_q[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst11|lpm_counter_component|auto_generated|safe_q[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst11|lpm_counter_component|auto_generated|safe_q[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst11|lpm_counter_component|auto_generated|safe_q[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst11|lpm_counter_component|auto_generated|safe_q[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst11|lpm_counter_component|auto_generated|safe_q[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst11|lpm_counter_component|auto_generated|safe_q[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst11|lpm_counter_component|auto_generated|safe_q[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst11|lpm_counter_component|auto_generated|safe_q[6]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst11|lpm_counter_component|auto_generated|safe_q[6]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst11|lpm_counter_component|auto_generated|safe_q[7]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst11|lpm_counter_component|auto_generated|safe_q[7]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst11|lpm_counter_component|auto_generated|safe_q[8]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst11|lpm_counter_component|auto_generated|safe_q[8]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst11|lpm_counter_component|auto_generated|safe_q[9]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst11|lpm_counter_component|auto_generated|safe_q[9]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst11|lpm_counter_component|auto_generated|safe_q[10]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst11|lpm_counter_component|auto_generated|safe_q[10]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|58~147_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst1|58~147_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst6|2|3~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst6|2|3~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst11|lpm_counter_component|auto_generated|safe_q[11]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst11|lpm_counter_component|auto_generated|safe_q[11]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst7|15|3~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst7|15|3~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst6|19|3~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst6|19|3~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|op_1~218_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|op_1~218_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst6|18|3~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst6|18|3~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst6|15|3~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst6|15|3~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst6|10|3~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst6|10|3~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst6|3|3~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst6|3|3~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|op_1~213_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|op_1~213_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|op_1~208_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|op_1~208_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|op_1~203_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|op_1~203_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|op_1~198_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|op_1~198_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|op_1~193_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|op_1~193_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst7|3|3~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst7|3|3~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst7|2|3~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst7|2|3~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst6|25|3~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst6|25|3~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst6|24|3~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst6|24|3~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|op_1~188_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|op_1~188_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|op_1~183_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|op_1~183_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|op_1~178_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|op_1~178_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|op_1~173_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|op_1~173_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|op_1~168_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|op_1~168_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|op_1~163_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|op_1~163_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|aeb_int~74_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst18|lpm_compare_component|auto_generated|aeb_int~74_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|inst|lpm_ff_component|dffs[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|inst|lpm_ff_component|dffs[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \addr[9]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \addrSet[0]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \addrSet[5]~I_modesel\ : std_logic_vector(26 DOWNTO 0);