twice.vhd

来自「FPGA 实现基于ISA接口的3路编码器计数」· VHDL 代码 · 共 33 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity twice is
	port(	clk		:in		std_logic;
			--rst		:in		std_logic;
			clk_out	:out	std_logic);
end twice;

architecture rtl of twice is
	signal clk_temp	:	std_logic;
	signal d_out	:	std_logic;
	signal d_outn	:	std_logic;
	
begin
process(clk_temp)
begin
	--if(rst = '1') then
	--	d_out <= '0';
	--else
		if(clk_temp'event and clk_temp = '1') then
			d_out <= d_outn;
		end if;
	--end if;
end process;

clk_temp <= clk xor d_out;
clk_out <= clk_temp;
d_outn <= not d_out;

end rtl;