5050pwm.vho

FPGA 实现基于ISA接口的3路编码器计数

SIGNAL \inst5|COUNTER[24]~1537\ : std_logic;
SIGNAL \inst5|COUNTER[24]~1537COUT1_1592\ : std_logic;
SIGNAL \inst5|COUNTER[25]~1532\ : std_logic;
SIGNAL \inst5|COUNTER~1549\ : std_logic;
SIGNAL \inst5|COUNTER~1554\ : std_logic;
SIGNAL \inst5|COUNTER~1557\ : std_logic;
SIGNAL \inst5|COUNTER~1562\ : std_logic;
SIGNAL \inst5|COUNTER[26]~1529\ : std_logic;
SIGNAL \inst5|COUNTER[26]~1529COUT1_1593\ : std_logic;
SIGNAL \inst5|COUNTER[27]~1524\ : std_logic;
SIGNAL \inst5|COUNTER[27]~1524COUT1_1594\ : std_logic;
SIGNAL \inst5|COUNTER[28]~1521\ : std_logic;
SIGNAL \inst5|COUNTER[28]~1521COUT1_1595\ : std_logic;
SIGNAL \inst5|COUNTER[29]~1516\ : std_logic;
SIGNAL \inst5|COUNTER[29]~1516COUT1_1596\ : std_logic;
SIGNAL \inst5|COUNTER[30]~1513\ : std_logic;
SIGNAL \inst5|comb~2107\ : std_logic;
SIGNAL \inst5|comb~2037\ : std_logic;
SIGNAL \inst5|comb~2038\ : std_logic;
SIGNAL \inst5|comb~2039\ : std_logic;
SIGNAL \inst5|comb~2040\ : std_logic;
SIGNAL \inst5|comb~2048\ : std_logic;
SIGNAL \RD~combout\ : std_logic;
SIGNAL \inst5|comb~2049\ : std_logic;
SIGNAL \inst5|comb~2050\ : std_logic;
SIGNAL \inst5|DATA_OUT[7]$latch\ : std_logic;
SIGNAL \inst5|comb~49\ : std_logic;
SIGNAL \inst5|comb_1011\ : std_logic;
SIGNAL \inst5|comb~2054\ : std_logic;
SIGNAL \inst5|comb~2055\ : std_logic;
SIGNAL \inst5|comb~2056\ : std_logic;
SIGNAL \inst5|comb~2057\ : std_logic;
SIGNAL \inst5|comb~2051\ : std_logic;
SIGNAL \inst5|comb~2052\ : std_logic;
SIGNAL \inst5|comb~2053\ : std_logic;
SIGNAL \inst5|comb~2058\ : std_logic;
SIGNAL \inst5|DATA_OUT[6]$latch\ : std_logic;
SIGNAL \inst5|comb~2059\ : std_logic;
SIGNAL \inst5|comb~2060\ : std_logic;
SIGNAL \inst5|comb~2061\ : std_logic;
SIGNAL \inst5|comb~2062\ : std_logic;
SIGNAL \inst5|comb~2063\ : std_logic;
SIGNAL \inst5|comb~2064\ : std_logic;
SIGNAL \inst5|comb~2065\ : std_logic;
SIGNAL \inst5|comb~2066\ : std_logic;
SIGNAL \inst5|DATA_OUT[5]$latch\ : std_logic;
SIGNAL \inst5|comb~2070\ : std_logic;
SIGNAL \inst5|comb~2071\ : std_logic;
SIGNAL \inst5|comb~2072\ : std_logic;
SIGNAL \inst5|comb~2073\ : std_logic;
SIGNAL \inst5|comb~2067\ : std_logic;
SIGNAL \inst5|comb~2068\ : std_logic;
SIGNAL \inst5|comb~2069\ : std_logic;
SIGNAL \inst5|comb~2074\ : std_logic;
SIGNAL \inst5|DATA_OUT[4]$latch\ : std_logic;
SIGNAL \inst5|comb~2075\ : std_logic;
SIGNAL \inst5|comb~2076\ : std_logic;
SIGNAL \inst5|comb~2077\ : std_logic;
SIGNAL \inst5|comb~2078\ : std_logic;
SIGNAL \inst5|comb~2079\ : std_logic;
SIGNAL \inst5|comb~2080\ : std_logic;
SIGNAL \inst5|comb~2081\ : std_logic;
SIGNAL \inst5|comb~2082\ : std_logic;
SIGNAL \inst5|DATA_OUT[3]$latch\ : std_logic;
SIGNAL \inst5|comb~2083\ : std_logic;
SIGNAL \inst5|comb~2084\ : std_logic;
SIGNAL \inst5|comb~2085\ : std_logic;
SIGNAL \inst5|comb~2086\ : std_logic;
SIGNAL \inst5|comb~2087\ : std_logic;
SIGNAL \inst5|comb~2088\ : std_logic;
SIGNAL \inst5|comb~2089\ : std_logic;
SIGNAL \inst5|comb~2090\ : std_logic;
SIGNAL \inst5|DATA_OUT[2]$latch\ : std_logic;
SIGNAL \inst5|comb~2091\ : std_logic;
SIGNAL \inst5|comb~2092\ : std_logic;
SIGNAL \inst5|comb~2093\ : std_logic;
SIGNAL \inst5|comb~2094\ : std_logic;
SIGNAL \inst5|comb~2095\ : std_logic;
SIGNAL \inst5|comb~2096\ : std_logic;
SIGNAL \inst5|comb~2097\ : std_logic;
SIGNAL \inst5|comb~2098\ : std_logic;
SIGNAL \inst5|DATA_OUT[1]$latch\ : std_logic;
SIGNAL \inst5|comb~2102\ : std_logic;
SIGNAL \inst5|comb~2103\ : std_logic;
SIGNAL \inst5|comb~2104\ : std_logic;
SIGNAL \inst5|comb~2105\ : std_logic;
SIGNAL \inst5|comb~2099\ : std_logic;
SIGNAL \inst5|comb~2100\ : std_logic;
SIGNAL \inst5|comb~2101\ : std_logic;
SIGNAL \inst5|comb~2106\ : std_logic;
SIGNAL \inst5|DATA_OUT[0]$latch\ : std_logic;
SIGNAL \inst5|COUNTER\ : std_logic_vector(31 DOWNTO 0);
SIGNAL \inst5|COUNTER2\ : std_logic_vector(31 DOWNTO 0);
SIGNAL \inst5|COUNTER3\ : std_logic_vector(31 DOWNTO 0);
SIGNAL \inst5|SENSOR_AB\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \inst5|SENSOR_AB2\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \inst5|SENSOR_AB3\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \inst|inst11|lpm_counter_component|auto_generated|safe_q\ : std_logic_vector(11 DOWNTO 0);
SIGNAL \inst|inst|lpm_ff_component|dffs\ : std_logic_vector(0 DOWNTO 0);
SIGNAL DD : std_logic_vector(7 DOWNTO 0);
SIGNAL \addr~combout\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \addrSet~combout\ : std_logic_vector(5 DOWNTO 0);
SIGNAL \inst8|inst11|lpm_counter_component|auto_generated|safe_q\ : std_logic_vector(11 DOWNTO 0);
SIGNAL \inst8|inst|lpm_ff_component|dffs\ : std_logic_vector(0 DOWNTO 0);
SIGNAL \inst7|inst11|lpm_counter_component|auto_generated|safe_q\ : std_logic_vector(11 DOWNTO 0);
SIGNAL \inst7|inst|lpm_ff_component|dffs\ : std_logic_vector(0 DOWNTO 0);
SIGNAL \inst6|ALT_INV_48~44\ : std_logic;
SIGNAL \ALT_INV_WR~combout\ : std_logic;

BEGIN

PWMout <= ww_PWMout;
ww_WR <= WR;
ww_addr <= addr;
ww_clock <= clock;
ww_PHA0 <= PHA0;
ww_PHB0 <= PHB0;
ww_PHA1 <= PHA1;
ww_PHB1 <= PHB1;
ww_PHA2 <= PHA2;
ww_PHB2 <= PHB2;
ww_RD <= RD;
EN <= ww_EN;
ww_addrSet <= addrSet;
ww_AEN <= AEN;
PWMen <= ww_PWMen;
LED2en <= ww_LED2en;
PWMout1 <= ww_PWMout1;
PWMout0 <= ww_PWMout0;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\inst2|altpll_component|pll_INCLK_bus\ <= (gnd & \clock~combout\);

\inst2|altpll_component|_clk0\ <= \inst2|altpll_component|pll_CLK_bus\(0);
\inst2|altpll_component|pll~CLK1\ <= \inst2|altpll_component|pll_CLK_bus\(1);
\inst2|altpll_component|pll~CLK2\ <= \inst2|altpll_component|pll_CLK_bus\(2);
\inst2|altpll_component|pll~CLK3\ <= \inst2|altpll_component|pll_CLK_bus\(3);
\inst2|altpll_component|pll~CLK4\ <= \inst2|altpll_component|pll_CLK_bus\(4);
\inst2|altpll_component|pll~CLK5\ <= \inst2|altpll_component|pll_CLK_bus\(5);
\inst6|ALT_INV_48~44\ <= NOT \inst6|48~44\;
\ALT_INV_WR~combout\ <= NOT \WR~combout\;

\D[7]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "bidir",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \inst5|DATA_OUT[7]$latch\,
	oe => \inst5|comb_1011\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	padio => D(7),
	combout => DD(7));

\D[6]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "bidir",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \inst5|DATA_OUT[6]$latch\,
	oe => \inst5|comb_1011\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	padio => D(6),
	combout => DD(6));

\D[5]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "bidir",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \inst5|DATA_OUT[5]$latch\,
	oe => \inst5|comb_1011\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	padio => D(5),
	combout => DD(5));

\D[4]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "bidir",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \inst5|DATA_OUT[4]$latch\,
	oe => \inst5|comb_1011\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	padio => D(4),
	combout => DD(4));

\D[3]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "bidir",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \inst5|DATA_OUT[3]$latch\,
	oe => \inst5|comb_1011\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	padio => D(3),
	combout => DD(3));

\D[2]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "bidir",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \inst5|DATA_OUT[2]$latch\,
	oe => \inst5|comb_1011\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,