5050pwm.map.rpt

FPGA 实现基于ISA接口的3路编码器计数

; Remove Duplicate Logic                                             ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                ; Off                ;
; Perform gate-level register retiming                               ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;
; Auto ROM Replacement                                               ; On                 ; On                 ;
; Auto RAM Replacement                                               ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto RAM Block Balancing                                           ; On                 ; On                 ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M512 Memory Blocks                               ; Unlimited          ; Unlimited          ;
; Maximum Number of M4K Memory Blocks                                ; Unlimited          ; Unlimited          ;
; Maximum Number of M-RAM Memory Blocks                              ; Unlimited          ; Unlimited          ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                        ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                        ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+
; 5050PWM.bdf                      ; yes             ; User Block Diagram/Schematic File  ; D:/FPGA/5050PWM_V54/5050PWM.bdf                                     ;
; pwm.bdf                          ; yes             ; Other                              ; D:/FPGA/5050PWM_V54/pwm.bdf                                         ;
; lpm_dff0.vhd                     ; yes             ; Other                              ; D:/FPGA/5050PWM_V54/lpm_dff0.vhd                                    ;
; lpm_ff.tdf                       ; yes             ; Megafunction                       ; c:/altera/quartus60/libraries/megafunctions/lpm_ff.tdf              ;
; lpm_constant.inc                 ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/lpm_constant.inc        ;
; aglobal60.inc                    ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/aglobal60.inc           ;
; lpm_compare1.vhd                 ; yes             ; Other                              ; D:/FPGA/5050PWM_V54/lpm_compare1.vhd                                ;
; lpm_compare.tdf                  ; yes             ; Megafunction                       ; c:/altera/quartus60/libraries/megafunctions/lpm_compare.tdf         ;
; comptree.inc                     ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/comptree.inc            ;
; altshift.inc                     ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/altshift.inc            ;
; db/cmpr_deg.tdf                  ; yes             ; Auto-Generated Megafunction        ; D:/FPGA/5050PWM_V54/db/cmpr_deg.tdf                                 ;
; lpm_counter0.vhd                 ; yes             ; Other                              ; D:/FPGA/5050PWM_V54/lpm_counter0.vhd                                ;
; lpm_counter.tdf                  ; yes             ; Megafunction                       ; c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf         ;
; lpm_decode.inc                   ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/lpm_decode.inc          ;
; lpm_add_sub.inc                  ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.inc         ;
; cmpconst.inc                     ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/cmpconst.inc            ;
; lpm_compare.inc                  ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/lpm_compare.inc         ;
; lpm_counter.inc                  ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/lpm_counter.inc         ;
; dffeea.inc                       ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/dffeea.inc              ;
; alt_synch_counter.inc            ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/alt_synch_counter.inc   ;
; alt_synch_counter_f.inc          ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc            ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.inc   ;
; alt_counter_stratix.inc          ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/alt_counter_stratix.inc ;
; db/cntr_gth.tdf                  ; yes             ; Auto-Generated Megafunction        ; D:/FPGA/5050PWM_V54/db/cntr_gth.tdf                                 ;
; 74377b.bdf                       ; yes             ; Megafunction                       ; c:/altera/quartus60/libraries/others/maxplus2/74377b.bdf            ;
; enadff.bdf                       ; yes             ; Megafunction                       ; c:/altera/quartus60/libraries/others/maxplus2/enadff.bdf            ;
; 16ndmux.bdf                      ; yes             ; Megafunction                       ; c:/altera/quartus60/libraries/others/maxplus2/16ndmux.bdf           ;
; myPLL.vhd                        ; yes             ; Other                              ; D:/FPGA/5050PWM_V54/myPLL.vhd                                       ;
; altpll.tdf                       ; yes             ; Megafunction                       ; c:/altera/quartus60/libraries/megafunctions/altpll.tdf              ;
; stratix_pll.inc                  ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/stratix_pll.inc         ;
; stratixii_pll.inc                ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/stratixii_pll.inc       ;
; cycloneii_pll.inc                ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/cycloneii_pll.inc       ;
; CLOCK_MY.vhd                     ; yes             ; Other                              ; D:/FPGA/5050PWM_V54/CLOCK_MY.vhd                                    ;
; 74688.bdf                        ; yes             ; Megafunction                       ; c:/altera/quartus60/libraries/others/maxplus2/74688.bdf             ;
; 74377.bdf                        ; yes             ; Megafunction                       ; c:/altera/quartus60/libraries/others/maxplus2/74377.bdf             ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 452   ;
;     -- Combinational with no register       ; 268   ;
;     -- Register only                        ; 49    ;
;     -- Combinational with a register        ; 135   ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 94    ;
;     -- 3 input functions                    ; 155   ;
;     -- 2 input functions                    ; 148   ;
;     -- 1 input functions                    ; 6     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 293   ;
;     -- arithmetic mode                      ; 159   ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 108   ;
;                                             ;       ;
; Total registers                             ; 184   ;
; Total logic cells in carry chains           ; 168   ;
; I/O pins                                    ; 40    ;
; Total PLLs                                  ; 1     ;
; Maximum fan-out node                        ; WR    ;
; Maximum fan-out                             ; 148   ;
; Total fan-out                               ; 1748  ;
; Average fan-out                             ; 3.55  ;