5050pwm.map.rpt

FPGA 实现基于ISA接口的3路编码器计数

Analysis & Synthesis report for 5050PWM
Mon Jul 07 15:30:01 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. User-Specified and Inferred Latches
  8. General Register Statistics
  9. Multiplexer Restructuring Statistics (Restructuring Performed)
 10. Parameter Settings for User Entity Instance: pwm:inst|lpm_dff0:inst|lpm_ff:lpm_ff_component
 11. Parameter Settings for User Entity Instance: pwm:inst|lpm_compare1:inst18|lpm_compare:lpm_compare_component
 12. Parameter Settings for User Entity Instance: pwm:inst|lpm_counter0:inst11|lpm_counter:lpm_counter_component
 13. Parameter Settings for User Entity Instance: myPLL:inst2|altpll:altpll_component
 14. Parameter Settings for User Entity Instance: pwm:inst7|lpm_dff0:inst|lpm_ff:lpm_ff_component
 15. Parameter Settings for User Entity Instance: pwm:inst7|lpm_compare1:inst18|lpm_compare:lpm_compare_component
 16. Parameter Settings for User Entity Instance: pwm:inst7|lpm_counter0:inst11|lpm_counter:lpm_counter_component
 17. Parameter Settings for User Entity Instance: pwm:inst8|lpm_dff0:inst|lpm_ff:lpm_ff_component
 18. Parameter Settings for User Entity Instance: pwm:inst8|lpm_compare1:inst18|lpm_compare:lpm_compare_component
 19. Parameter Settings for User Entity Instance: pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component
 20. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Jul 07 15:30:01 2008    ;
; Quartus II Version          ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name               ; 5050PWM                                  ;
; Top-level Entity Name       ; 5050PWM                                  ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 452                                      ;
; Total pins                  ; 40                                       ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 0                                        ;
; Total PLLs                  ; 1                                        ;
+-----------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP1C6Q240C8        ;                    ;
; Top-level entity name                                              ; 5050PWM            ; 5050PWM            ;
; Family name                                                        ; Cyclone            ; Stratix            ;
; Type of Retiming Performed During Resynthesis                      ; Full               ;                    ;
; Resynthesis Optimization Effort                                    ; Normal             ;                    ;
; Physical Synthesis Level for Resynthesis                           ; Normal             ;                    ;
; Use Generated Physical Constraints File                            ; On                 ;                    ;
; Use smart compilation                                              ; Off                ; Off                ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                ; Off                ;
; Optimization Technique -- Cyclone                                  ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                 ; 70                 ;
; Auto Carry Chains                                                  ; On                 ; On                 ;
; Auto Open-Drain Pins                                               ; On                 ; On                 ;