5050pwm.fit.rpt

FPGA 实现基于ISA接口的3路编码器计数

Fitter report for 5050PWM
Mon Jul 07 15:30:13 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Pin-Out File
  5. Fitter Resource Usage Summary
  6. Input Pins
  7. Output Pins
  8. Bidir Pins
  9. I/O Bank Usage
 10. All Package Pins
 11. PLL Summary
 12. PLL Usage
 13. Output Pin Default Load For Reported TCO
 14. Fitter Resource Utilization by Entity
 15. Delay Chain Summary
 16. Pad To Core Delay Chain Fanout
 17. Control Signals
 18. Global & Other Fast Signals
 19. Non-Global High Fan-Out Signals
 20. Interconnect Usage Summary
 21. LAB Logic Elements
 22. LAB-wide Signals
 23. LAB Signals Sourced
 24. LAB Signals Sourced Out
 25. LAB Distinct Inputs
 26. Fitter Device Options
 27. Advanced Data - General
 28. Advanced Data - Placement Preparation
 29. Advanced Data - Placement
 30. Advanced Data - Routing
 31. Fitter Messages
 32. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------+
; Fitter Summary                                                   ;
+-----------------------+------------------------------------------+
; Fitter Status         ; Successful - Mon Jul 07 15:30:13 2008    ;
; Quartus II Version    ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name         ; 5050PWM                                  ;
; Top-level Entity Name ; 5050PWM                                  ;
; Family                ; Cyclone                                  ;
; Device                ; EP1C6Q240C8                              ;
; Timing Models         ; Final                                    ;
; Total logic elements  ; 434 / 5,980 ( 7 % )                      ;
; Total pins            ; 40 / 185 ( 22 % )                        ;
; Total virtual pins    ; 0                                        ;
; Total memory bits     ; 0 / 92,160 ( 0 % )                       ;
; Total PLLs            ; 1 / 2 ( 50 % )                           ;
+-----------------------+------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                      ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Option                                             ; Setting                        ; Default Value                  ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Device                                             ; EP1C6Q240C8                    ;                                ;
; Use smart compilation                              ; Off                            ; Off                            ;
; Router Timing Optimization Level                   ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                           ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                        ; Off                            ; Off                            ;
; Optimize Timing                                    ; Normal compilation             ; Normal compilation             ;