5050pwm.tan.rpt

FPGA 实现基于ISA接口的3路编码器计数

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+----------------------------------------------------------+-----------+-----------------------------------+----------------------------------+----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+-------------------------------------------+-------------------------------------------+--------------+
; Type                                                     ; Slack     ; Required Time                     ; Actual Time                      ; From                                                                                               ; To                                                                                                 ; From Clock                                ; To Clock                                  ; Failed Paths ;
+----------------------------------------------------------+-----------+-----------------------------------+----------------------------------+----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+-------------------------------------------+-------------------------------------------+--------------+
; Worst-case tsu                                           ; N/A       ; None                              ; 10.086 ns                        ; addr[2]                                                                                            ; CLOCK_MY:inst5|DATA_OUT[4]$latch                                                                   ; --                                        ; addr[0]                                   ; 0            ;
; Worst-case tco                                           ; N/A       ; None                              ; 17.029 ns                        ; CLOCK_MY:inst5|comb_1011                                                                           ; D[3]                                                                                               ; RD                                        ; --                                        ; 0            ;
; Worst-case tpd                                           ; N/A       ; None                              ; 14.869 ns                        ; addrSet[0]                                                                                         ; EN                                                                                                 ; --                                        ; --                                        ; 0            ;
; Worst-case th                                            ; N/A       ; None                              ; 1.818 ns                         ; addr[3]                                                                                            ; CLOCK_MY:inst5|DATA_OUT[7]$latch                                                                   ; --                                        ; RD                                        ; 0            ;
; Clock Setup: 'myPLL:inst2|altpll:altpll_component|_clk0' ; 5.332 ns  ; 100.00 MHz ( period = 10.000 ns ) ; 214.22 MHz ( period = 4.668 ns ) ; pwm:inst7|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[6]  ; pwm:inst7|lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[0]                                            ; myPLL:inst2|altpll:altpll_component|_clk0 ; myPLL:inst2|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'clock'                                     ; 33.989 ns ; 25.00 MHz ( period = 40.000 ns )  ; 166.36 MHz ( period = 6.011 ns ) ; CLOCK_MY:inst5|SENSOR_AB[1]                                                                        ; CLOCK_MY:inst5|COUNTER[31]                                                                         ; clock                                     ; clock                                     ; 0            ;
; Clock Hold: 'clock'                                      ; 1.031 ns  ; 25.00 MHz ( period = 40.000 ns )  ; N/A                              ; CLOCK_MY:inst5|COUNTER[31]                                                                         ; CLOCK_MY:inst5|COUNTER[31]                                                                         ; clock                                     ; clock                                     ; 0            ;
; Clock Hold: 'myPLL:inst2|altpll:altpll_component|_clk0'  ; 1.045 ns  ; 100.00 MHz ( period = 10.000 ns ) ; N/A                              ; pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] ; pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11] ; myPLL:inst2|altpll:altpll_component|_clk0 ; myPLL:inst2|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                             ;           ;                                   ;                                  ;                                                                                                    ;                                                                                                    ;                                           ;                                           ; 0            ;
+----------------------------------------------------------+-----------+-----------------------------------+----------------------------------+----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+-------------------------------------------+-------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+