📄 mypll_waveforms.html
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<title>Sample Waveforms for myPLL.vhd </title>
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<h2><CENTER>Sample behavioral waveforms for design file myPLL.vhd </CENTER></h2>
<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design myPLL.vhd. The design myPLL.vhd has Cyclone AUTO pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 40000 ps. CLK0 multiply by = 4, CLK0 divide by = 1, CLK0 phase_shift = 0 </P>
<CENTER><img src=myPLL_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing NORMAL mode operation. </CENTER></P>
<P><FONT size=3></P>
<P></P>
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