5050pwm.map.summary

FPGA 实现基于ISA接口的3路编码器计数

Analysis & Synthesis Status : Successful - Mon Jul 07 15:30:01 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : 5050PWM
Top-level Entity Name : 5050PWM
Family : Cyclone
Total logic elements : 452
Total pins : 40
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 1