📄 seriesparallel.rpt
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_LC3_L36 = DFFE( _EQ022, GLOBAL( clk), VCC, VCC, VCC);
_EQ022 = _LC3_L36 & !_LC5_L36 & !_LC7_L27 & !_LC7_L36
# !_LC3_L36 & _LC5_L36 & _LC7_L27 & _LC7_L36;
-- Node name is '|controller:2|:9' = '|controller:2|st_d'
-- Equation name is '_LC1_L49', type is buried
_LC1_L49 = DFFE( st, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|controller:2|~11~1'
-- Equation name is '_LC3_L27', type is buried
-- synthesized logic cell
_LC3_L27 = LCELL( _EQ023);
_EQ023 = _LC2_L36 & _LC2_L49 & !_LC3_L36 & !_LC7_L27;
-- Node name is '|controller:2|:11'
-- Equation name is '_LC2_L49', type is buried
!_LC2_L49 = _LC2_L49~NOT;
_LC2_L49~NOT = LCELL( _EQ024);
_EQ024 = _LC1_L49
# !st;
-- Node name is '|controller:2|~211~1'
-- Equation name is '_LC1_L36', type is buried
-- synthesized logic cell
_LC1_L36 = LCELL( _EQ025);
_EQ025 = _LC3_L36 & !_LC5_L36 & !_LC7_L27 & !_LC7_L36
# !_LC3_L36 & !_LC7_L27 & _LC7_L36
# !_LC3_L36 & _LC5_L36 & !_LC7_L27;
-- Node name is '|controller:2|~211~2'
-- Equation name is '_LC4_L36', type is buried
-- synthesized logic cell
_LC4_L36 = LCELL( _EQ026);
_EQ026 = !_LC3_L36 & _LC7_L27;
-- Node name is '|controller:2|~266~1'
-- Equation name is '_LC2_L36', type is buried
-- synthesized logic cell
_LC2_L36 = LCELL( _EQ027);
_EQ027 = !_LC5_L36 & !_LC7_L36;
-- Node name is '|controller:2|~266~2'
-- Equation name is '_LC5_L27', type is buried
-- synthesized logic cell
!_LC5_L27 = _LC5_L27~NOT;
_LC5_L27~NOT = LCELL( _EQ028);
_EQ028 = _LC2_L36 & _LC3_L36;
-- Node name is '|controller:2|:266'
-- Equation name is '_LC6_L27', type is buried
!_LC6_L27 = _LC6_L27~NOT;
_LC6_L27~NOT = LCELL( _EQ029);
_EQ029 = !_LC2_L36 & _LC3_L36
# _LC7_L27 & _LC8_L36
# _LC2_L36 & !_LC3_L36 & _LC8_L36
# _LC2_L36 & !_LC3_L36 & !_LC7_L27
# _LC3_L36 & _LC7_L27;
-- Node name is '|controller:2|:302'
-- Equation name is '_LC6_L36', type is buried
!_LC6_L36 = _LC6_L36~NOT;
_LC6_L36~NOT = LCELL( _EQ030);
_EQ030 = !_LC8_L36
# !_LC7_L27
# _LC3_L36;
-- Node name is '|controller:2|:328'
-- Equation name is '_LC8_L27', type is buried
_LC8_L27 = DFFE( _EQ031, GLOBAL( clk), VCC, VCC, VCC);
_EQ031 = !_LC5_L27 & _LC7_L27
# !_LC2_L49 & _LC8_L27;
-- Node name is '|LPM_ADD_SUB:4|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_L31', type is buried
_LC1_L31 = LCELL( _EQ032);
_EQ032 = _LC3_L31 & _LC4_L31
# _LC3_L31 & _LC6_L31
# _LC4_L31 & _LC6_L31;
-- Node name is '|LPM_ADD_SUB:4|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_L46', type is buried
_LC4_L46 = LCELL( _EQ033);
_EQ033 = _LC1_L31 & _LC2_L27
# _LC1_L31 & _LC3_L46
# _LC2_L27 & _LC3_L46;
-- Node name is '|LPM_ADD_SUB:4|addcore:adder|pcarry3' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC5_L46', type is buried
_LC5_L46 = LCELL( _EQ034);
_EQ034 = _LC2_L46 & _LC4_L46
# _LC4_L30 & _LC4_L46
# _LC2_L46 & _LC4_L30;
-- Node name is '|LPM_ADD_SUB:4|addcore:adder|:48' from file "addcore.tdf" line 308, column 28
-- Equation name is '_LC6_L31', type is buried
_LC6_L31 = LCELL( _EQ035);
_EQ035 = _LC2_L31 & _LC5_L31;
-- Node name is '|LPM_DFF:3|dffs0' from file "lpm_dff.tdf" line 64, column 7
-- Equation name is '_LC5_L31', type is buried
_LC5_L31 = DFFE( data0, GLOBAL( clk), VCC, VCC, enable);
-- Node name is '|LPM_DFF:3|dffs1' from file "lpm_dff.tdf" line 64, column 7
-- Equation name is '_LC4_L31', type is buried
_LC4_L31 = DFFE( data1, GLOBAL( clk), VCC, VCC, enable);
-- Node name is '|LPM_DFF:3|dffs2' from file "lpm_dff.tdf" line 64, column 7
-- Equation name is '_LC3_L46', type is buried
_LC3_L46 = DFFE( data2, GLOBAL( clk), VCC, VCC, enable);
-- Node name is '|LPM_DFF:3|dffs3' from file "lpm_dff.tdf" line 64, column 7
-- Equation name is '_LC4_L30', type is buried
_LC4_L30 = DFFE( data3, GLOBAL( clk), VCC, VCC, enable);
-- Node name is '|8dff:5|:1' = '|8dff:5|Q1'
-- Equation name is '_LC5_L51', type is buried
!_LC5_L51 = _LC5_L51~NOT;
_LC5_L51~NOT = DFFE(!_LC8_L36, GLOBAL( clk), _LC8_L27, VCC, VCC);
-- Node name is '|8dff:5|:9' = '|8dff:5|Q2'
-- Equation name is '_LC7_L51', type is buried
!_LC7_L51 = _LC7_L51~NOT;
_LC7_L51~NOT = DFFE(!_LC1_L52, GLOBAL( clk), _LC8_L27, VCC, VCC);
-- Node name is '|8dff:5|:12' = '|8dff:5|Q3'
-- Equation name is '_LC5_L52', type is buried
!_LC5_L52 = _LC5_L52~NOT;
_LC5_L52~NOT = DFFE(!_LC4_L52, GLOBAL( clk), _LC8_L27, VCC, VCC);
-- Node name is '|8dff:5|:15' = '|8dff:5|Q4'
-- Equation name is '_LC7_L52', type is buried
!_LC7_L52 = _LC7_L52~NOT;
_LC7_L52~NOT = DFFE(!_LC8_L52, GLOBAL( clk), _LC8_L27, VCC, VCC);
-- Node name is '|8dff:5|:18' = '|8dff:5|Q5'
-- Equation name is '_LC4_L51', type is buried
!_LC4_L51 = _LC4_L51~NOT;
_LC4_L51~NOT = DFFE(!_LC2_L31, GLOBAL( clk), _LC8_L27, VCC, VCC);
-- Node name is '|8dff:5|:21' = '|8dff:5|Q6'
-- Equation name is '_LC2_L51', type is buried
!_LC2_L51 = _LC2_L51~NOT;
_LC2_L51~NOT = DFFE(!_LC3_L31, GLOBAL( clk), _LC8_L27, VCC, VCC);
-- Node name is '|8dff:5|:24' = '|8dff:5|Q7'
-- Equation name is '_LC4_L27', type is buried
!_LC4_L27 = _LC4_L27~NOT;
_LC4_L27~NOT = DFFE(!_LC2_L27, GLOBAL( clk), _LC8_L27, VCC, VCC);
-- Node name is '|8dff:5|:27' = '|8dff:5|Q8'
-- Equation name is '_LC1_L27', type is buried
!_LC1_L27 = _LC1_L27~NOT;
_LC1_L27~NOT = DFFE(!_LC2_L46, GLOBAL( clk), _LC8_L27, VCC, VCC);
Project Information c:\maxplus2\verilog9\seriesparallel.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:05
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:07
Memory Allocated
-----------------
Peak memory allocated during compilation = 53,506K
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