seriesparallel.rpt

ｖｅｒｉｌｏｇ實現算術運算後利用7段顯示器將結果輸出

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Device-Specific Information:           c:\maxplus2\verilog9\seriesparallel.rpt
seriesparallel

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       27         clk


Device-Specific Information:           c:\maxplus2\verilog9\seriesparallel.rpt
seriesparallel

** CLEAR SIGNALS **

Type     Fan-out       Name
DFF         10         |controller:2|:328


Device-Specific Information:           c:\maxplus2\verilog9\seriesparallel.rpt
seriesparallel

** EQUATIONS **

clk      : INPUT;
data0    : INPUT;
data1    : INPUT;
data2    : INPUT;
data3    : INPUT;
enable   : INPUT;
mult0    : INPUT;
mult1    : INPUT;
mult2    : INPUT;
mult3    : INPUT;
st       : INPUT;

-- Node name is 'done' 
-- Equation name is 'done', type is output 
done     =  _LC8_L27;

-- Node name is 'q0' 
-- Equation name is 'q0', type is output 
q0       =  _LC5_L51;

-- Node name is 'q1' 
-- Equation name is 'q1', type is output 
q1       =  _LC7_L51;

-- Node name is 'q2' 
-- Equation name is 'q2', type is output 
q2       =  _LC5_L52;

-- Node name is 'q3' 
-- Equation name is 'q3', type is output 
q3       =  _LC7_L52;

-- Node name is 'q4' 
-- Equation name is 'q4', type is output 
q4       =  _LC4_L51;

-- Node name is 'q5' 
-- Equation name is 'q5', type is output 
q5       =  _LC2_L51;

-- Node name is 'q6' 
-- Equation name is 'q6', type is output 
q6       =  _LC4_L27;

-- Node name is 'q7' 
-- Equation name is 'q7', type is output 
q7       =  _LC1_L27;

-- Node name is '|acc:1|:70' 
-- Equation name is '_LC6_L46', type is buried 
_LC6_L46 = LCELL( _EQ001);
  _EQ001 =  _LC5_L46 &  _LC6_L36
         # !_LC6_L36 &  _LC7_L46;

-- Node name is '|acc:1|:71' 
-- Equation name is '_LC8_L46', type is buried 
_LC8_L46 = LCELL( _EQ002);
  _EQ002 =  _LC2_L46 & !_LC4_L30 & !_LC4_L46
         # !_LC2_L46 &  _LC4_L30 & !_LC4_L46 &  _LC6_L36
         #  _LC2_L46 &  _LC4_L30 &  _LC4_L46
         # !_LC2_L46 & !_LC4_L30 &  _LC4_L46 &  _LC6_L36
         #  _LC2_L46 & !_LC6_L36;

-- Node name is '|acc:1|:72' 
-- Equation name is '_LC1_L46', type is buried 
_LC1_L46 = LCELL( _EQ003);
  _EQ003 = !_LC1_L31 &  _LC2_L27 & !_LC3_L46
         # !_LC1_L31 & !_LC2_L27 &  _LC3_L46 &  _LC6_L36
         #  _LC1_L31 &  _LC2_L27 &  _LC3_L46
         #  _LC1_L31 & !_LC2_L27 & !_LC3_L46 &  _LC6_L36
         #  _LC2_L27 & !_LC6_L36;

-- Node name is '|acc:1|:73' 
-- Equation name is '_LC8_L31', type is buried 
_LC8_L31 = LCELL( _EQ004);
  _EQ004 =  _LC3_L31 &  _LC4_L31 &  _LC6_L31
         #  _LC3_L31 & !_LC4_L31 & !_LC6_L31
         # !_LC3_L31 & !_LC4_L31 &  _LC6_L31 &  _LC6_L36
         # !_LC3_L31 &  _LC4_L31 & !_LC6_L31 &  _LC6_L36
         #  _LC3_L31 & !_LC6_L36;

-- Node name is '|acc:1|:74' 
-- Equation name is '_LC7_L31', type is buried 
_LC7_L31 = LCELL( _EQ005);
  _EQ005 =  _LC2_L31 & !_LC5_L31
         # !_LC2_L31 &  _LC5_L31 &  _LC6_L36
         #  _LC2_L31 & !_LC6_L36;

-- Node name is '|acc:1|:93' 
-- Equation name is '_LC6_L52', type is buried 
_LC6_L52 = LCELL( _EQ006);
  _EQ006 =  _LC2_L31 &  _LC6_L27
         # !_LC6_L27 &  _LC8_L52;

-- Node name is '|acc:1|:94' 
-- Equation name is '_LC3_L52', type is buried 
_LC3_L52 = LCELL( _EQ007);
  _EQ007 =  _LC6_L27 &  _LC8_L52
         #  _LC4_L52 & !_LC6_L27;

-- Node name is '|acc:1|:95' 
-- Equation name is '_LC2_L52', type is buried 
_LC2_L52 = LCELL( _EQ008);
  _EQ008 =  _LC4_L52 &  _LC6_L27
         #  _LC1_L52 & !_LC6_L27;

-- Node name is '|acc:1|:96' 
-- Equation name is '_LC3_L51', type is buried 
_LC3_L51 = LCELL( _EQ009);
  _EQ009 =  _LC1_L52 &  _LC6_L27
         # !_LC6_L27 &  _LC8_L36;

-- Node name is '|acc:1|:115' 
-- Equation name is '_LC7_L46', type is buried 
_LC7_L46 = DFFE( _EQ010, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ010 = !_LC2_L49 & !_LC6_L27 &  _LC6_L46;

-- Node name is '|acc:1|:116' 
-- Equation name is '_LC2_L46', type is buried 
_LC2_L46 = DFFE( _EQ011, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ011 = !_LC2_L49 &  _LC6_L27 &  _LC7_L46
         # !_LC2_L49 & !_LC6_L27 &  _LC8_L46;

-- Node name is '|acc:1|:117' 
-- Equation name is '_LC2_L27', type is buried 
_LC2_L27 = DFFE( _EQ012, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ012 =  _LC2_L46 & !_LC2_L49 &  _LC6_L27
         #  _LC1_L46 & !_LC2_L49 & !_LC6_L27;

-- Node name is '|acc:1|:118' 
-- Equation name is '_LC3_L31', type is buried 
_LC3_L31 = DFFE( _EQ013, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ013 =  _LC2_L27 & !_LC2_L49 &  _LC6_L27
         # !_LC2_L49 & !_LC6_L27 &  _LC8_L31;

-- Node name is '|acc:1|:119' 
-- Equation name is '_LC2_L31', type is buried 
_LC2_L31 = DFFE( _EQ014, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ014 = !_LC2_L49 &  _LC3_L31 &  _LC6_L27
         # !_LC2_L49 & !_LC6_L27 &  _LC7_L31;

-- Node name is '|acc:1|:120' 
-- Equation name is '_LC8_L52', type is buried 
_LC8_L52 = DFFE( _EQ015, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ015 = !_LC2_L49 &  _LC6_L52
         #  _LC2_L49 &  mult3;

-- Node name is '|acc:1|:121' 
-- Equation name is '_LC4_L52', type is buried 
_LC4_L52 = DFFE( _EQ016, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ016 = !_LC2_L49 &  _LC3_L52
         #  _LC2_L49 &  mult2;

-- Node name is '|acc:1|:122' 
-- Equation name is '_LC1_L52', type is buried 
_LC1_L52 = DFFE( _EQ017, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ017 = !_LC2_L49 &  _LC2_L52
         #  _LC2_L49 &  mult1;

-- Node name is '|acc:1|:123' 
-- Equation name is '_LC8_L36', type is buried 
_LC8_L36 = DFFE( _EQ018, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ018 = !_LC2_L49 &  _LC3_L51
         #  _LC2_L49 &  mult0;

-- Node name is '|controller:2|:215' = '|controller:2|state0' 
-- Equation name is '_LC7_L27', type is buried 
_LC7_L27 = DFFE( _EQ019, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ019 =  _LC3_L27
         #  _LC1_L36
         #  _LC4_L36 & !_LC8_L36;

-- Node name is '|controller:2|:214' = '|controller:2|state1' 
-- Equation name is '_LC5_L36', type is buried 
_LC5_L36 = DFFE( _EQ020, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ020 = !_LC3_L36 & !_LC5_L36 &  _LC7_L27
         # !_LC3_L36 &  _LC5_L36 & !_LC7_L27;

-- Node name is '|controller:2|:213' = '|controller:2|state2' 
-- Equation name is '_LC7_L36', type is buried 
_LC7_L36 = DFFE( _EQ021, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ021 = !_LC3_L36 &  _LC5_L36 &  _LC7_L27 & !_LC7_L36
         # !_LC3_L36 & !_LC7_L27 &  _LC7_L36
         # !_LC3_L36 & !_LC5_L36 &  _LC7_L36;

-- Node name is '|controller:2|:212' = '|controller:2|state3' 
-- Equation name is '_LC3_L36', type is buried