📄 seriesparallel.rpt
字号:
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
L27 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 8/26( 30%)
L30 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/26( 7%)
L31 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 7/26( 26%)
L36 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 4/26( 15%)
L46 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 8/26( 30%)
L49 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/26( 3%)
L51 5/ 8( 62%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 6/26( 23%)
L52 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 7/26( 26%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 14/327 ( 4%)
Total logic cells used: 48/4992 ( 0%)
Total embedded cells used: 0/192 ( 0%)
Total EABs used: 0/12 ( 0%)
Average fan-in: 2.72/4 ( 68%)
Total fan-in: 131/19968 ( 0%)
Total input pins required: 11
Total input I/O cell registers required: 0
Total output pins required: 9
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 48
Total flipflops required: 27
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 5/4992 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 EA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
G: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
H: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
I: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
J: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
K: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
L: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 1 8 0 0 0 0 8 0 0 0 0 0 0 0 0 0 8 0 0 2 0 5 8 48/0
Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 1 8 0 0 0 0 8 0 0 0 0 0 0 0 0 0 8 0 0 2 0 5 8 48/0
Device-Specific Information: c:\maxplus2\verilog9\seriesparallel.rpt
seriesparallel
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
D12 - - - -- INPUT G ^ 0 0 0 0 clk
V11 - - - -- INPUT ^ 0 0 0 1 data0
R12 - - - -- INPUT ^ 0 0 0 1 data1
P11 - - - -- INPUT ^ 0 0 0 1 data2
R13 - - - 28 INPUT ^ 0 0 0 1 data3
E12 - - - -- INPUT ^ 0 0 0 4 enable
V21 - - L -- INPUT ^ 0 0 0 1 mult0
V1 - - L -- INPUT ^ 0 0 0 1 mult1
V6 - - L -- INPUT ^ 0 0 0 1 mult2
V2 - - L -- INPUT ^ 0 0 0 1 mult3
H11 - - - -- INPUT ^ 0 0 0 2 st
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\maxplus2\verilog9\seriesparallel.rpt
seriesparallel
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
T17 - - L -- OUTPUT 0 1 0 0 done
R16 - - L -- OUTPUT 0 1 0 0 q0
W2 - - L -- OUTPUT 0 1 0 0 q1
T18 - - L -- OUTPUT 0 1 0 0 q2
V20 - - L -- OUTPUT 0 1 0 0 q3
T19 - - K -- OUTPUT 0 1 0 0 q4
H13 - - L -- OUTPUT 0 1 0 0 q5
U3 - - L -- OUTPUT 0 1 0 0 q6
U19 - - L -- OUTPUT 0 1 0 0 q7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\maxplus2\verilog9\seriesparallel.rpt
seriesparallel
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - L 46 OR2 0 3 0 1 |acc:1|:70
- 8 - L 46 OR2 0 4 0 1 |acc:1|:71
- 1 - L 46 OR2 0 4 0 1 |acc:1|:72
- 8 - L 31 OR2 0 4 0 1 |acc:1|:73
- 7 - L 31 OR2 0 3 0 1 |acc:1|:74
- 6 - L 52 OR2 0 3 0 1 |acc:1|:93
- 3 - L 52 OR2 0 3 0 1 |acc:1|:94
- 2 - L 52 OR2 0 3 0 1 |acc:1|:95
- 3 - L 51 OR2 0 3 0 1 |acc:1|:96
- 7 - L 46 DFFE + 0 3 0 2 |acc:1|:115
- 2 - L 46 DFFE + 0 4 0 4 |acc:1|:116
- 2 - L 27 DFFE + 0 4 0 4 |acc:1|:117
- 3 - L 31 DFFE + 0 4 0 4 |acc:1|:118
- 2 - L 31 DFFE + 0 4 0 4 |acc:1|:119
- 8 - L 52 DFFE + 1 2 0 3 |acc:1|:120
- 4 - L 52 DFFE + 1 2 0 3 |acc:1|:121
- 1 - L 52 DFFE + 1 2 0 3 |acc:1|:122
- 8 - L 36 DFFE + 1 2 0 5 |acc:1|:123
- 1 - L 49 DFFE + 1 0 0 1 |controller:2|st_d (|controller:2|:9)
- 3 - L 27 AND2 s 0 4 0 1 |controller:2|~11~1
- 2 - L 49 OR2 ! 1 1 0 11 |controller:2|:11
- 1 - L 36 OR2 s 0 4 0 1 |controller:2|~211~1
- 4 - L 36 AND2 s 0 2 0 1 |controller:2|~211~2
- 3 - L 36 DFFE + 0 3 0 8 |controller:2|state3 (|controller:2|:212)
- 7 - L 36 DFFE + 0 3 0 3 |controller:2|state2 (|controller:2|:213)
- 5 - L 36 DFFE + 0 2 0 4 |controller:2|state1 (|controller:2|:214)
- 7 - L 27 DFFE + 0 4 0 9 |controller:2|state0 (|controller:2|:215)
- 2 - L 36 AND2 s 0 2 0 3 |controller:2|~266~1
- 5 - L 27 AND2 s ! 0 2 0 1 |controller:2|~266~2
- 6 - L 27 OR2 ! 0 4 0 9 |controller:2|:266
- 6 - L 36 OR2 ! 0 3 0 5 |controller:2|:302
- 8 - L 27 DFFE + 0 3 1 8 |controller:2|:328
- 1 - L 31 OR2 0 3 0 2 |LPM_ADD_SUB:4|addcore:adder|pcarry1
- 4 - L 46 OR2 0 3 0 2 |LPM_ADD_SUB:4|addcore:adder|pcarry2
- 5 - L 46 OR2 0 3 0 1 |LPM_ADD_SUB:4|addcore:adder|pcarry3
- 6 - L 31 AND2 0 2 0 2 |LPM_ADD_SUB:4|addcore:adder|:48
- 5 - L 31 DFFE + 2 0 0 2 |LPM_DFF:3|dffs0
- 4 - L 31 DFFE + 2 0 0 2 |LPM_DFF:3|dffs1
- 3 - L 46 DFFE + 2 0 0 2 |LPM_DFF:3|dffs2
- 4 - L 30 DFFE + 2 0 0 2 |LPM_DFF:3|dffs3
- 5 - L 51 DFFE + ! 0 2 1 0 |8dff:5|Q1 (|8dff:5|:1)
- 7 - L 51 DFFE + ! 0 2 1 0 |8dff:5|Q2 (|8dff:5|:9)
- 5 - L 52 DFFE + ! 0 2 1 0 |8dff:5|Q3 (|8dff:5|:12)
- 7 - L 52 DFFE + ! 0 2 1 0 |8dff:5|Q4 (|8dff:5|:15)
- 4 - L 51 DFFE + ! 0 2 1 0 |8dff:5|Q5 (|8dff:5|:18)
- 2 - L 51 DFFE + ! 0 2 1 0 |8dff:5|Q6 (|8dff:5|:21)
- 4 - L 27 DFFE + ! 0 2 1 0 |8dff:5|Q7 (|8dff:5|:24)
- 1 - L 27 DFFE + ! 0 2 1 0 |8dff:5|Q8 (|8dff:5|:27)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: c:\maxplus2\verilog9\seriesparallel.rpt
seriesparallel
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
I: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
J: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
K: 0/208( 0%) 0/104( 0%) 1/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
L: 26/208( 12%) 0/104( 0%) 6/104( 5%) 4/16( 25%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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