controller.rpt

ｖｅｒｉｌｏｇ實現算術運算後利用7段顯示器將結果輸出

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Device-Specific Information:               c:\maxplus2\verilog9\controller.rpt
controller

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT        6         clk


Device-Specific Information:               c:\maxplus2\verilog9\controller.rpt
controller

** EQUATIONS **

clk      : INPUT;
m        : INPUT;
st       : INPUT;

-- Node name is 'ad' 
-- Equation name is 'ad', type is output 
ad       =  _LC1_G29;

-- Node name is 'done' 
-- Equation name is 'done', type is output 
done     =  _LC5_G46;

-- Node name is 'load' 
-- Equation name is 'load', type is output 
load     =  _LC8_G42;

-- Node name is 'sh' 
-- Equation name is 'sh', type is output 
sh       =  _LC8_G29;

-- Node name is ':215' = 'state0' 
-- Equation name is 'state0', location is LC3_G29, type is buried.
state0   = DFFE( _EQ001, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 =  _LC2_G29 &  _LC8_G42
         #  _LC8_G46
         #  _LC5_G29;

-- Node name is ':214' = 'state1' 
-- Equation name is 'state1', location is LC4_G46, type is buried.
state1   = DFFE( _EQ002, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ002 = !state0 &  state1 & !state3
         #  state0 & !state1 & !state3;

-- Node name is ':213' = 'state2' 
-- Equation name is 'state2', location is LC2_G46, type is buried.
state2   = DFFE( _EQ003, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 =  state0 &  state1 & !state2 & !state3
         # !state0 &  state2 & !state3
         # !state1 &  state2 & !state3;

-- Node name is ':212' = 'state3' 
-- Equation name is 'state3', location is LC1_G46, type is buried.
state3   = DFFE( _EQ004, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ004 = !state0 & !state1 & !state2 &  state3
         #  state0 &  state1 &  state2 & !state3;

-- Node name is ':9' = 'st_d' 
-- Equation name is 'st_d', location is LC1_G42, type is buried.
st_d     = DFFE( st, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':11' 
-- Equation name is '_LC8_G42', type is buried 
_LC8_G42 = LCELL( _EQ005);
  _EQ005 =  st & !st_d;

-- Node name is '~211~1' 
-- Equation name is '~211~1', location is LC8_G46, type is buried.
-- synthesized logic cell 
_LC8_G46 = LCELL( _EQ006);
  _EQ006 = !state0 &  state1 & !state3
         # !state0 &  state2 & !state3
         # !state0 & !state1 & !state2 &  state3;

-- Node name is '~211~2' 
-- Equation name is '~211~2', location is LC5_G29, type is buried.
-- synthesized logic cell 
_LC5_G29 = LCELL( _EQ007);
  _EQ007 =  _LC4_G29 & !m;

-- Node name is '~261~1' 
-- Equation name is '~261~1', location is LC4_G29, type is buried.
-- synthesized logic cell 
_LC4_G29 = LCELL( _EQ008);
  _EQ008 =  state0 & !state3;

-- Node name is '~266~1' 
-- Equation name is '~266~1', location is LC3_G46, type is buried.
-- synthesized logic cell 
!_LC3_G46 = _LC3_G46~NOT;
_LC3_G46~NOT = LCELL( _EQ009);
  _EQ009 = !state1 & !state2;

-- Node name is '~266~2' 
-- Equation name is '~266~2', location is LC2_G29, type is buried.
-- synthesized logic cell 
_LC2_G29 = LCELL( _EQ010);
  _EQ010 = !_LC3_G46 & !state0 & !state3;

-- Node name is '~266~3' 
-- Equation name is '~266~3', location is LC6_G46, type is buried.
-- synthesized logic cell 
_LC6_G46 = LCELL( _EQ011);
  _EQ011 = !_LC3_G46 &  state3;

-- Node name is ':266' 
-- Equation name is '_LC8_G29', type is buried 
_LC8_G29 = LCELL( _EQ012);
  _EQ012 = !_LC3_G46 & !state0 &  state3
         #  _LC3_G46 & !state0 & !state3
         # !m &  state0 & !state3;

-- Node name is ':302' 
-- Equation name is '_LC1_G29', type is buried 
_LC1_G29 = LCELL( _EQ013);
  _EQ013 =  m &  state0 & !state3;

-- Node name is ':328' 
-- Equation name is '_LC5_G46', type is buried 
_LC5_G46 = DFFE( _EQ014, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ014 =  _LC6_G46 &  state0
         #  _LC5_G46 & !_LC8_G42;



Project Information                        c:\maxplus2\verilog9\controller.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:05
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:06


Memory Allocated
-----------------

Peak memory allocated during compilation  = 51,431K