📄 acc.rpt
字号:
cm : INPUT;
load : INPUT;
multiplier0 : INPUT;
multiplier1 : INPUT;
multiplier2 : INPUT;
multiplier3 : INPUT;
sh : INPUT;
sum0 : INPUT;
sum1 : INPUT;
sum2 : INPUT;
sum3 : INPUT;
-- Node name is 'pro0'
-- Equation name is 'pro0', type is output
pro0 = _LC1_A25;
-- Node name is 'pro1'
-- Equation name is 'pro1', type is output
pro1 = _LC3_L9;
-- Node name is 'pro2'
-- Equation name is 'pro2', type is output
pro2 = _LC5_L9;
-- Node name is 'pro3'
-- Equation name is 'pro3', type is output
pro3 = _LC4_L9;
-- Node name is 'pro4'
-- Equation name is 'pro4', type is output
pro4 = _LC2_L9;
-- Node name is 'pro5'
-- Equation name is 'pro5', type is output
pro5 = _LC3_I40;
-- Node name is 'pro6'
-- Equation name is 'pro6', type is output
pro6 = _LC5_I40;
-- Node name is 'pro7'
-- Equation name is 'pro7', type is output
pro7 = _LC8_I40;
-- Node name is 'pro8'
-- Equation name is 'pro8', type is output
pro8 = _LC1_I40;
-- Node name is ':71'
-- Equation name is '_LC6_I40', type is buried
_LC6_I40 = LCELL( _EQ001);
_EQ001 = !ad & _LC8_I40
# ad & sum3;
-- Node name is ':72'
-- Equation name is '_LC4_I40', type is buried
_LC4_I40 = LCELL( _EQ002);
_EQ002 = !ad & _LC5_I40
# ad & sum2;
-- Node name is ':73'
-- Equation name is '_LC2_I40', type is buried
_LC2_I40 = LCELL( _EQ003);
_EQ003 = !ad & _LC3_I40
# ad & sum1;
-- Node name is ':74'
-- Equation name is '_LC8_L9', type is buried
_LC8_L9 = LCELL( _EQ004);
_EQ004 = !ad & _LC2_L9
# ad & sum0;
-- Node name is ':93'
-- Equation name is '_LC7_L9', type is buried
_LC7_L9 = LCELL( _EQ005);
_EQ005 = _LC4_L9 & !sh
# _LC2_L9 & sh;
-- Node name is ':94'
-- Equation name is '_LC6_L9', type is buried
_LC6_L9 = LCELL( _EQ006);
_EQ006 = _LC5_L9 & !sh
# _LC4_L9 & sh;
-- Node name is ':95'
-- Equation name is '_LC1_L9', type is buried
_LC1_L9 = LCELL( _EQ007);
_EQ007 = _LC3_L9 & !sh
# _LC5_L9 & sh;
-- Node name is ':96'
-- Equation name is '_LC2_A25', type is buried
_LC2_A25 = LCELL( _EQ008);
_EQ008 = _LC3_L9 & sh
# _LC1_A25 & !sh;
-- Node name is '~97~1'
-- Equation name is '~97~1', location is LC7_I40, type is buried.
-- synthesized logic cell
_LC7_I40 = LCELL( _EQ009);
_EQ009 = !load & !sh;
-- Node name is ':115'
-- Equation name is '_LC1_I40', type is buried
_LC1_I40 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = !ad & _LC1_I40 & _LC7_I40
# ad & cm & _LC7_I40;
-- Node name is ':116'
-- Equation name is '_LC8_I40', type is buried
_LC8_I40 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = _LC6_I40 & !load & !sh
# _LC1_I40 & !load & sh;
-- Node name is ':117'
-- Equation name is '_LC5_I40', type is buried
_LC5_I40 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = _LC4_I40 & !load & !sh
# _LC8_I40 & !load & sh;
-- Node name is ':118'
-- Equation name is '_LC3_I40', type is buried
_LC3_I40 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = _LC2_I40 & !load & !sh
# _LC5_I40 & !load & sh;
-- Node name is ':119'
-- Equation name is '_LC2_L9', type is buried
_LC2_L9 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = _LC8_L9 & !load & !sh
# _LC3_I40 & !load & sh;
-- Node name is ':120'
-- Equation name is '_LC4_L9', type is buried
_LC4_L9 = DFFE( _EQ015, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = _LC7_L9 & !load
# load & multiplier3;
-- Node name is ':121'
-- Equation name is '_LC5_L9', type is buried
_LC5_L9 = DFFE( _EQ016, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = _LC6_L9 & !load
# load & multiplier2;
-- Node name is ':122'
-- Equation name is '_LC3_L9', type is buried
_LC3_L9 = DFFE( _EQ017, GLOBAL( clk), VCC, VCC, VCC);
_EQ017 = _LC1_L9 & !load
# load & multiplier1;
-- Node name is ':123'
-- Equation name is '_LC1_A25', type is buried
_LC1_A25 = DFFE( _EQ018, GLOBAL( clk), VCC, VCC, VCC);
_EQ018 = _LC2_A25 & !load
# load & multiplier0;
Project Information c:\maxplus2\verilog9\acc.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:05
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:06
Memory Allocated
-----------------
Peak memory allocated during compilation = 52,523K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -