📄 acc.rpt
字号:
Project Information c:\maxplus2\verilog9\acc.rpt
MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 05/24/2007 03:14:29
Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
acc EP1K100FC484-3 13 9 0 0 0 % 18 0 %
User Pins: 13 9 0
Project Information c:\maxplus2\verilog9\acc.rpt
** PROJECT TIMING MESSAGES **
Warning: Timing characteristics of device EP1K100FC484-3 are preliminary
Device-Specific Information: c:\maxplus2\verilog9\acc.rpt
acc
***** Logic for device 'acc' compiled without errors.
Device: EP1K100FC484-3
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
----------------------------------------------------------------------
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 |
|AB o o o o o o o o o o o o o o o o o o o o o o AB|
|AA o o o o o o o o o o o o o o o o o o o o o o AA|
|Y o o o o o o o o o o o o o o o o o o o o o o Y|
|W o o o o o o o o o o o o o o o o o o o o o o W|
|V o o o o o o o o o o o o o o o o o o o o o o V|
|U o o o o o o o o o o o o o o o o o o o o o o U|
|T o o o o o o o o o o o o o o o o o o o o o o T|
|R o o o o o o o o o o o o o o o o o o o o o o R|
|P o o o o o o o o o o o o o o o o o o o o o o P|
|N o o o o o o o o o o o o o o o o o o o o o o N|
|M o o o o o o o o o o o o o o o o o o o o o o M|
|L o o o o o o o o o o o o o o o o o o o o o o L|
|K o o o o o o o o o o o o o o o o o o o o o o K|
|J o o o o o o o o o o o o o o o o o o o o o o J|
|H o o o o o o o o o o o o o o o o o o o o o o H|
|G o o o o o o o o o o o o o o o o o o o o o o G|
|F o o o o o o o o o o o o o o o o o o o o o o F|
|E o o o o o o o o o o o o o o o o o o o o o o E|
|D o o o o o o o o o o o o o o o o o o o o o o D|
|C o o o o o o o o o o o o o o o o o o o o o o C|
|B o o o o o o o o o o o o o o o o o o o o o o B|
|A o o o o o o o o o o o o o o o o o o o o o o A|
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 |
----------------------------------------------------------------------
EP1K100FC484-3
Bottom View
Device-Specific Information: c:\maxplus2\verilog9\acc.rpt
acc
A1 GND E10 RESERVED J19 RESERVED P6 RESERVED V15 RESERVED
A2 N.C. E11 RESERVED J20 GND P7 RESERVED V16 pro5
A3 N.C. E12 sh J21 RESERVED P8 VCCINT V17 RESERVED
A4 N.C. E13 RESERVED J22 RESERVED P9 GND V18 RESERVED
A5 N.C. E14 RESERVED K1 RESERVED P10 VCCINT V19 #TRST
A6 VCCIO E15 RESERVED K2 N.C. P11 multiplier1 V20 multiplier2
A7 RESERVED E16 RESERVED K3 GND P12 VCCINT V21 RESERVED
A8 GND E17 RESERVED K4 RESERVED P13 VCCIO V22 VCCIO
A9 RESERVED E18 #TCK K5 RESERVED P14 GND W1 pro2
A10 RESERVED E19 ^nCEO K6 RESERVED P15 VCCINT W2 RESERVED
A11 RESERVED E20 RESERVED K7 RESERVED P16 RESERVED W3 RESERVED
A12 RESERVED E21 GND K8 RESERVED P17 RESERVED W4 RESERVED
A13 VCCIO E22 RESERVED K9 VCCIO P18 pro7 W5 RESERVED
A14 RESERVED F1 RESERVED K10 GND P19 RESERVED W6 RESERVED
A15 RESERVED F2 N.C. K11 VCCIO P20 N.C. W7 RESERVED
A16 RESERVED F3 RESERVED K12 GND P21 pro8 W8 RESERVED
A17 RESERVED F4 RESERVED K13 GND P22 N.C. W9 RESERVED
A18 RESERVED F5 #TDI K14 VCCIO R1 VCCIO W10 RESERVED
A19 RESERVED F6 RESERVED K15 RESERVED R2 RESERVED W11 GND
A20 RESERVED F7 RESERVED K16 RESERVED R3 N.C. W12 RESERVED
A21 RESERVED F8 RESERVED K17 RESERVED R4 RESERVED W13 RESERVED
A22 GND F9 RESERVED K18 RESERVED R5 RESERVED W14 RESERVED
B1 GND F10 GND K19 RESERVED R6 RESERVED W15 RESERVED
B2 GND F11 RESERVED K20 VCCIO R7 RESERVED W16 RESERVED
B3 N.C. F12 RESERVED K21 RESERVED R8 GND W17 RESERVED
B4 N.C. F13 RESERVED K22 RESERVED R9 VCCIO W18 RESERVED
B5 VCCIO F14 RESERVED L1 RESERVED R10 RESERVED W19 ^nSTATUS
B6 RESERVED F15 RESERVED L2 N.C. R11 RESERVED W20 GND
B7 RESERVED F16 RESERVED L3 RESERVED R12 ad W21 VCCINT
B8 RESERVED F17 RESERVED L4 RESERVED R13 RESERVED W22 N.C.
B9 RESERVED F18 ^CONF_DONE L5 RESERVED R14 VCCINT Y1 GND
B10 N.C. F19 #TDO L6 RESERVED R15 GND Y2 GND
B11 RESERVED F20 RESERVED L7 RESERVED R16 sum0 Y3 GND
B12 RESERVED F21 RESERVED L8 RESERVED R17 RESERVED Y4 RESERVED
B13 RESERVED F22 RESERVED L9 VCCINT R18 RESERVED Y5 RESERVED
B14 RESERVED G1 VCCIO L10 VCCINT R19 RESERVED Y6 RESERVED
B15 RESERVED G2 RESERVED L11 GND R20 RESERVED Y7 RESERVED
B16 RESERVED G3 GND L12 GND R21 RESERVED Y8 VCCINT
B17 GND G4 RESERVED L13 VCCINT R22 GND Y9 RESERVED
B18 RESERVED G5 RESERVED L14 VCCIO T1 GND Y10 RESERVED
B19 RESERVED G6 RESERVED L15 RESERVED T2 RESERVED Y11 RESERVED
B20 RESERVED G7 RESERVED L16 RESERVED T3 VCCIO Y12 RESERVED
B21 GND G8 RESERVED L17 RESERVED T4 RESERVED Y13 RESERVED
B22 GND G9 RESERVED L18 RESERVED T5 RESERVED Y14 RESERVED
C1 RESERVED G10 RESERVED L19 RESERVED T6 RESERVED Y15 RESERVED
C2 GND G11 RESERVED L20 RESERVED T7 ^nCONFIG Y16 N.C.
C3 RESERVED G12 RESERVED L21 RESERVED T8 RESERVED Y17 RESERVED
C4 RESERVED G13 RESERVED L22 RESERVED T9 RESERVED Y18 RESERVED
C5 RESERVED G14 RESERVED M1 RESERVED T10 RESERVED Y19 RESERVED
C6 RESERVED G15 VCCIO M2 RESERVED T11 RESERVED Y20 RESERVED
C7 RESERVED G16 RESERVED M3 RESERVED T12 RESERVED Y21 GND
C8 RESERVED G17 RESERVED M4 RESERVED T13 RESERVED Y22 GND
C9 RESERVED G18 RESERVED M5 RESERVED T14 RESERVED AA1 GND
C10 RESERVED G19 RESERVED M6 RESERVED T15 VCCIO AA2 RESERVED
C11 VCCINT G20 RESERVED M7 RESERVED T16 RESERVED AA3 RESERVED
C12 RESERVED G21 GND M8 RESERVED T17 RESERVED AA4 RESERVED
C13 RESERVED G22 RESERVED M9 VCCIO T18 RESERVED AA5 RESERVED
C14 RESERVED H1 RESERVED M10 VCCINT T19 RESERVED AA6 GND
C15 VCCINT H2 GND M11 GND T20 N.C. AA7 RESERVED
C16 RESERVED H3 RESERVED M12 GND T21 N.C. AA8 RESERVED
C17 N.C. H4 RESERVED M13 VCCINT T22 VCCIO AA9 RESERVED
C18 RESERVED H5 RESERVED M14 VCCINT U1 N.C. AA10 RESERVED
C19 RESERVED H6 RESERVED M15 pro6 U2 RESERVED AA11 RESERVED
C20 RESERVED H7 RESERVED M16 sum3 U3 pro3 AA12 VCCINT
C21 GND H8 GND M17 RESERVED U4 ^MSEL0 AA13 RESERVED
C22 RESERVED H9 VCCIO M18 RESERVED U5 RESERVED AA14 RESERVED
D1 RESERVED H10 RESERVED M19 RESERVED U6 RESERVED AA15 N.C.
D2 RESERVED H11 load M20 GND U7 RESERVED AA16 RESERVED
D3 pro0 H12 RESERVED M21 RESERVED U8 RESERVED AA17 RESERVED
D4 ^DATA0 H13 pro4 M22 RESERVED U9 RESERVED AA18 RESERVED
D5 RESERVED H14 VCCINT N1 N.C. U10 RESERVED AA19 RESERVED
D6 GND H15 GND N2 RESERVED U11 RESERVED AA20 RESERVED
D7 RESERVED H16 RESERVED N3 VCCIO U12 RESERVED AA21 RESERVED
D8 RESERVED H17 RESERVED N4 RESERVED U13 RESERVED AA22 GND
D9 RESERVED H18 RESERVED N5 RESERVED U14 RESERVED AB1 RESERVED
D10 RESERVED H19 RESERVED N6 RESERVED U15 RESERVED AB2 RESERVED
D11 RESERVED H20 VCCIO N7 RESERVED U16 RESERVED AB3 N.C.
D12 clk H21 RESERVED N8 GND U17 RESERVED AB4 N.C.
D13 RESERVED H22 RESERVED N9 VCCIO U18 #TMS AB5 N.C.
D14 RESERVED J1 RESERVED N10 GND U19 RESERVED AB6 RESERVED
D15 RESERVED J2 N.C. N11 VCCIO U20 RESERVED AB7 N.C.
D16 RESERVED J3 RESERVED N12 VCCINT U21 RESERVED AB8 RESERVED
D17 GND J4 RESERVED N13 GND U22 RESERVED AB9 RESERVED
D18 RESERVED J5 RESERVED N14 VCCIO V1 RESERVED AB10 RESERVED
D19 RESERVED J6 RESERVED N15 RESERVED V2 multiplier3AB11 GND
D20 RESERVED J7 RESERVED N16 RESERVED V3 GND AB12 RESERVED
D21 RESERVED J8 VCCINT N17 cm V4 ^MSEL1 AB13 VCCIO
D22 RESERVED J9 GND N18 RESERVED V5 VCCINT AB14 RESERVED
E1 VCCIO J10 VCCINT N19 RESERVED V6 RESERVED AB15 N.C.
E2 RESERVED J11 VCCIO N20 VCCIO V7 RESERVED AB16 GND
E3 RESERVED J12 VCCINT N21 RESERVED V8 RESERVED AB17 N.C.
E4 ^nCE J13 VCCIO N22 RESERVED V9 RESERVED AB18 N.C.
E5 ^DCLK J14 GND P1 RESERVED V10 RESERVED AB19 N.C.
E6 pro1 J15 VCCINT P2 RESERVED V11 multiplier0AB20 N.C.
E7 RESERVED J16 RESERVED P3 sum2 V12 RESERVED AB21 RESERVED
E8 RESERVED J17 RESERVED P4 GND V13 RESERVED AB22 RESERVED
E9 RESERVED J18 RESERVED P5 sum1 V14 RESERVED
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: c:\maxplus2\verilog9\acc.rpt
acc
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A25 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 4/26( 15%)
I40 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 7/26( 26%)
L9 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 8/26( 30%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 16/327 ( 4%)
Total logic cells used: 18/4992 ( 0%)
Total embedded cells used: 0/192 ( 0%)
Total EABs used: 0/12 ( 0%)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -