controller.v

来自「ｖｅｒｉｌｏｇ實現算術運算後利用7段顯示器將結果輸出」· Verilog 代码 · 共 60 行

module controller(clk,st,m,load,sh,ad,done);
input    clk,st,m;
output   done,load,sh,ad;
reg      done;
reg      [3:0] state;
reg      st_d;
wire     load,sh,ad;
parameter s0 = 4'b0000;
parameter s1 = 4'b0001;
parameter s2 = 4'b0010;
parameter s3 = 4'b0011;
parameter s4 = 4'b0100;
parameter s5 = 4'b0101;
parameter s6 = 4'b0110;
parameter s7 = 4'b0111;
parameter s8 = 4'b1000;
parameter s9 = 4'b1001;
always@(posedge clk)
st_d <= st;
assign load = (st&&(~st_d))?1:0;
always@(posedge clk)
begin
   if(state==s9)  done<=1;
   else   if(load==1)  done<=0;
          else done <= done;
end
assign ad = (((state==s1)||(state==s3)||(state==s5)||(state==s7))&&(m==1))?1:0;

assign sh = (((state==s2)||(state==s4)||(state==s6)||(state==s8))||
               (((state==s1)||(state==s3)||(state==s5)||(state==s7))&&(m==0)))?1:0;   
always@(posedge clk)
begin
case(state)
s0:state=(load==0)?s0:s1;
s1:begin
      if(m==1)   state = s2;
      else   state = s3;
   end
s2:state = s3;
s3:begin
      if(m==1)   state = s4;
      else   state = s5;
   end
s4:state = s5;
s5:begin
      if(m==1)   state = s6;
      else   state = s7;
   end
s6:state = s7;
s7:begin
      if(m==1)   state = s8;
      else   state = s9;
   end
s8:state = s9;
s9:state = s0;
default:state = s0;
endcase
end
endmodule