acc.v

来自「ｖｅｒｉｌｏｇ實現算術運算後利用7段顯示器將結果輸出」· Verilog 代码 · 共 22 行

module acc(clk,load,sh,ad,cm,sum,multiplier,pro);
input   clk,load,sh,ad,cm;
input   [3:0] sum,multiplier;
output  [8:0] pro;
reg     [8:0] pro;
always@(posedge clk)
begin
   if(load==1)
   begin
      pro[3:0]<=multiplier;
      pro[8:4]<=5'b0;
   end
   else if(sh==1)
      pro<=pro>>1;
      else if(ad==1)
         begin
            pro[7:4]<=sum;
            pro[8]<=cm;
         end
end
endmodule