decoder.rpt
来自「鍵盤掃描ｖｅｒｉｌｏｇ硬體驗證可以將開發版鍵盤功能使用」· RPT 代码 · 共 1,013 行 · 第 1/4 页
RPT
1,013 行
Total EABs used: 0/12 ( 0%)
Average fan-in: 3.43/4 ( 85%)
Total fan-in: 175/19968 ( 0%)
Total input pins required: 9
Total input I/O cell registers required: 0
Total output pins required: 4
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 51
Total flipflops required: 4
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 43/4992 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 EA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
G: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
H: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
I: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
J: 0 0 8 0 0 0 0 0 0 3 8 0 0 8 0 0 0 0 8 0 0 0 0 0 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 51/0
K: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
L: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 8 0 0 0 0 0 0 3 8 0 0 8 0 0 0 0 8 0 0 0 0 0 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 51/0
Device-Specific Information: c:\maxplus2\verilog8\decoder.rpt
decoder
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
R12 - - - -- INPUT ^ 0 0 0 16 col0
V11 - - - -- INPUT ^ 0 0 0 10 col1
E12 - - - -- INPUT ^ 0 0 0 11 col2
R4 - - J -- INPUT ^ 0 0 0 8 col3
R6 - - J -- INPUT ^ 0 0 0 6 row0
H11 - - - -- INPUT ^ 0 0 0 14 row1
P11 - - - -- INPUT ^ 0 0 0 11 row2
P16 - - J -- INPUT ^ 0 0 0 9 row3
D12 - - - -- INPUT G ^ 0 0 0 0 v
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\maxplus2\verilog8\decoder.rpt
decoder
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
T9 - - J -- OUTPUT 0 1 0 0 n0
N15 - - J -- OUTPUT 0 1 0 0 n1
T2 - - J -- OUTPUT 0 1 0 0 n2
R18 - - J -- OUTPUT 0 1 0 0 n3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\maxplus2\verilog8\decoder.rpt
decoder
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - J 03 OR2 s ! 1 1 0 2 col0~1
- 1 - J 10 AND2 s 2 0 0 2 col0~2
- 4 - J 14 AND2 s 4 0 0 2 col0~3
- 6 - J 14 AND2 s 3 1 0 1 col0~4
- 8 - J 11 AND2 s 4 0 0 1 row1~1
- 1 - J 14 AND2 s 2 1 0 1 row3~1
- 3 - J 19 AND2 s 3 1 0 1 row3~2
- 4 - J 26 AND2 s ! 1 1 0 1 ~14~1
- 7 - J 26 AND2 s ! 1 1 0 2 ~40~1
- 1 - J 11 AND2 s 4 0 0 2 ~53~1
- 4 - J 11 AND2 s ! 2 0 0 7 ~66~1
- 5 - J 11 OR2 s 0 2 0 2 ~92~1
- 6 - J 11 OR2 ! 3 1 0 1 :92
- 3 - J 11 OR2 s ! 3 0 0 3 ~105~1
- 2 - J 10 AND2 s 2 0 0 5 ~131~1
- 6 - J 03 OR2 s ! 2 0 0 3 ~131~2
- 1 - J 26 OR2 ! 1 3 0 2 :131
- 5 - J 26 AND2 s 3 1 0 2 ~144~1
- 5 - J 03 AND2 s 3 1 0 4 ~157~1
- 2 - J 03 OR2 s ! 2 1 0 1 ~157~2
- 2 - J 25 OR2 ! 1 2 0 1 :157
- 7 - J 03 AND2 s 2 0 0 5 ~170~1
- 8 - J 26 AND2 s 1 1 0 2 ~170~2
- 1 - J 03 OR2 s ! 2 2 0 1 ~170~3
- 8 - J 10 AND2 s ! 2 0 0 4 ~183~1
- 8 - J 03 AND2 s 3 0 0 2 ~183~2
- 1 - J 19 AND2 s 1 3 0 1 ~183~3
- 8 - J 25 AND2 3 1 0 2 :209
- 3 - J 26 OR2 s ! 0 4 0 3 ~236~1
- 4 - J 03 OR2 s 1 3 0 1 ~236~2
- 3 - J 25 AND2 s 0 4 0 2 ~236~3
- 7 - J 11 OR2 s 3 1 0 1 ~242~1
- 2 - J 11 OR2 s 2 2 0 1 ~242~2
- 6 - J 19 AND2 s 2 1 0 1 ~242~3
- 2 - J 26 OR2 s ! 1 3 0 2 ~245~1
- 1 - J 25 OR2 s 0 4 0 3 ~245~2
- 2 - J 19 OR2 s 1 3 0 2 ~245~3
- 4 - J 19 OR2 s 2 2 0 1 ~245~4
- 5 - J 19 OR2 s 1 3 0 1 ~245~5
- 6 - J 26 OR2 s 3 1 0 1 ~248~1
- 4 - J 25 OR2 s 0 4 0 1 ~248~2
- 5 - J 25 OR2 s 0 4 0 1 ~248~3
- 7 - J 25 AND2 s ! 0 4 0 2 ~248~4
- 2 - J 14 OR2 s 4 0 0 1 ~251~1
- 3 - J 14 OR2 s 1 3 0 1 ~251~2
- 5 - J 14 OR2 s 1 3 0 1 ~251~3
- 7 - J 14 OR2 s 2 2 0 1 ~251~4
- 8 - J 19 DFFE + 0 4 1 0 :254
- 7 - J 19 DFFE + 0 4 1 0 :255
- 6 - J 25 DFFE + 0 4 1 0 :256
- 8 - J 14 DFFE + 0 3 1 0 :257
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: c:\maxplus2\verilog8\decoder.rpt
decoder
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
I: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
J: 8/208( 3%) 22/104( 21%) 0/104( 0%) 3/16( 18%) 4/16( 25%) 0/16( 0%)
K: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
L: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
37: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
38: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
39: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
40: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
41: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
42: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
43: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
44: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
45: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
46: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
47: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
48: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
49: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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