keyscanner.rpt

鍵盤掃描ｖｅｒｉｌｏｇ硬體驗證可以將開發版鍵盤功能使用

-- Equation name is '_LC6_H47', type is buried 
-- synthesized logic cell 
_LC6_H47 = LCELL( _EQ037);
  _EQ037 =  _LC3_H26 &  _LC4_H20 &  _LC6_H17 & !_LC6_H19
         #  _LC3_H26 & !_LC4_H20 &  _LC6_H17 &  _LC6_H19;

-- Node name is '|decoder:26|~251~2' 
-- Equation name is '_LC7_H47', type is buried 
-- synthesized logic cell 
_LC7_H47 = LCELL( _EQ038);
  _EQ038 =  _LC4_H26 &  _LC4_H47 &  _LC8_H20
         #  _LC4_H26 &  _LC6_H47 &  _LC8_H20;

-- Node name is '|decoder:26|~251~3' 
-- Equation name is '_LC8_H47', type is buried 
-- synthesized logic cell 
_LC8_H47 = LCELL( _EQ039);
  _EQ039 =  _LC4_H20 &  _LC6_H49 & !_LC8_H20
         # !_LC3_H47 &  _LC4_H20 & !_LC8_H20;

-- Node name is '|decoder:26|:254' 
-- Equation name is '_LC2_H48', type is buried 
_LC2_H48 = DFFE( _EQ040,  _LC6_H36,  VCC,  VCC,  VCC);
  _EQ040 =  _LC4_H20 &  _LC8_H48
         #  _LC1_H50
         #  _LC1_H48;

-- Node name is '|decoder:26|:255' 
-- Equation name is '_LC2_H50', type is buried 
_LC2_H50 = DFFE( _EQ041,  _LC6_H36,  VCC,  VCC,  VCC);
  _EQ041 =  _LC1_H48
         #  _LC4_H20 &  _LC8_H50
         #  _LC5_H50;

-- Node name is '|decoder:26|:256' 
-- Equation name is '_LC8_H49', type is buried 
_LC8_H49 = DFFE( _EQ042,  _LC6_H36,  VCC,  VCC,  VCC);
  _EQ042 =  _LC3_H50
         #  _LC3_H49;

-- Node name is '|decoder:26|:257' 
-- Equation name is '_LC5_H47', type is buried 
_LC5_H47 = DFFE( _EQ043,  _LC6_H36,  VCC,  VCC,  VCC);
  _EQ043 =  _LC7_H49
         #  _LC7_H47
         #  _LC8_H47
         # !_LC5_H17;

-- Node name is '|scanner:20|:164' = '|scanner:20|state0' 
-- Equation name is '_LC5_H19', type is buried 
_LC5_H19 = DFFE( _EQ044, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ044 =  _LC1_H17
         # !_LC1_H26 &  _LC8_H36
         #  _LC7_H19;

-- Node name is '|scanner:20|:165' = '|scanner:20|state1' 
-- Equation name is '_LC1_H19', type is buried 
_LC1_H19 = DFFE( _EQ045, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ045 =  _LC7_H19
         #  _LC8_H19
         # !_LC1_H26 &  _LC7_H36;

-- Node name is '|scanner:20|:166' = '|scanner:20|state2' 
-- Equation name is '_LC2_H19', type is buried 
_LC2_H19 = DFFE( _EQ046, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ046 = !_LC2_H36
         #  _LC3_H19
         #  _LC1_H26 &  _LC4_H19;

-- Node name is '|scanner:20|:38' 
-- Equation name is '_LC8_H36', type is buried 
_LC8_H36 = LCELL( _EQ047);
  _EQ047 =  _LC1_H19 & !_LC2_H19 & !_LC5_H19;

-- Node name is '|scanner:20|:60' 
-- Equation name is '_LC2_H17', type is buried 
_LC2_H17 = LCELL( _EQ048);
  _EQ048 =  _LC1_H19 &  _LC2_H19 & !_LC5_H19;

-- Node name is '|scanner:20|:82' 
-- Equation name is '_LC3_H36', type is buried 
_LC3_H36 = LCELL( _EQ049);
  _EQ049 = !_LC1_H19 & !_LC2_H19 &  _LC5_H19;

-- Node name is '|scanner:20|:111' 
-- Equation name is '_LC1_H36', type is buried 
_LC1_H36 = LCELL( _EQ050);
  _EQ050 =  _LC1_H19 & !_LC2_H19 &  _LC5_H19;

-- Node name is '|scanner:20|:145' 
-- Equation name is '_LC7_H19', type is buried 
_LC7_H19 = LCELL( _EQ051);
  _EQ051 =  _LC1_H36 & !_LC2_H26
         # !_LC1_H26 &  _LC1_H36;

-- Node name is '|scanner:20|:153' 
-- Equation name is '_LC2_H36', type is buried 
!_LC2_H36 = _LC2_H36~NOT;
_LC2_H36~NOT = LCELL( _EQ052);
  _EQ052 = !_LC1_H36 &  _LC5_H36;

-- Node name is '|scanner:20|~159~1' 
-- Equation name is '_LC4_H36', type is buried 
-- synthesized logic cell 
!_LC4_H36 = _LC4_H36~NOT;
_LC4_H36~NOT = LCELL( _EQ053);
  _EQ053 =  _LC1_H19 &  _LC5_H19
         # !_LC2_H19 &  _LC5_H19
         # !_LC1_H19 & !_LC5_H19
         # !_LC1_H19 & !_LC2_H19
         #  _LC2_H19 & !_LC5_H19
         #  _LC1_H19 &  _LC2_H19;

-- Node name is '|scanner:20|~159~2' 
-- Equation name is '_LC8_H19', type is buried 
-- synthesized logic cell 
_LC8_H19 = LCELL( _EQ054);
  _EQ054 = !_LC1_H19 &  _LC2_H19 & !_LC2_H26
         # !_LC1_H19 &  _LC2_H19 &  _LC5_H19
         #  _LC1_H19 & !_LC2_H19 & !_LC5_H19;

-- Node name is '|scanner:20|~159~3' 
-- Equation name is '_LC7_H36', type is buried 
-- synthesized logic cell 
_LC7_H36 = LCELL( _EQ055);
  _EQ055 =  _LC1_H19 &  _LC2_H19 & !_LC5_H19
         #  _LC3_H36;

-- Node name is '|scanner:20|~160~1' 
-- Equation name is '_LC3_H19', type is buried 
-- synthesized logic cell 
_LC3_H19 = LCELL( _EQ056);
  _EQ056 = !_LC1_H19 &  _LC2_H26 & !_LC5_H19
         # !_LC1_H19 & !_LC2_H19 & !_LC5_H19;

-- Node name is '|scanner:20|~160~2' 
-- Equation name is '_LC4_H19', type is buried 
-- synthesized logic cell 
_LC4_H19 = LCELL( _EQ057);
  _EQ057 =  _LC8_H36
         #  _LC3_H36
         #  _LC1_H36 &  _LC2_H26;

-- Node name is '|scanner:20|~201~1' 
-- Equation name is '_LC1_H17', type is buried 
-- synthesized logic cell 
_LC1_H17 = LCELL( _EQ058);
  _EQ058 =  _LC1_H19 &  _LC2_H19 & !_LC5_H19
         # !_LC1_H19 &  _LC5_H19;

-- Node name is '|scanner:20|:201' 
-- Equation name is '_LC6_H17', type is buried 
_LC6_H17 = LCELL( _EQ059);
  _EQ059 = !_LC1_H36 &  _LC5_H36 &  _LC6_H17
         #  _LC1_H17;

-- Node name is '|scanner:20|:202' 
-- Equation name is '_LC4_H20', type is buried 
_LC4_H20 = LCELL( _EQ060);
  _EQ060 = !_LC2_H36 &  _LC4_H20
         #  _LC4_H36
         #  _LC3_H36;

-- Node name is '|scanner:20|:203' 
-- Equation name is '_LC8_H20', type is buried 
_LC8_H20 = LCELL( _EQ061);
  _EQ061 = !_LC2_H36 &  _LC8_H20
         #  _LC2_H17
         #  _LC4_H36;

-- Node name is '|scanner:20|:204' 
-- Equation name is '_LC6_H19', type is buried 
_LC6_H19 = LCELL( _EQ062);
  _EQ062 = !_LC2_H36 &  _LC6_H19
         #  _LC7_H36
         #  _LC8_H36;

-- Node name is '|scanner:20|~217~1' 
-- Equation name is '_LC5_H36', type is buried 
-- synthesized logic cell 
_LC5_H36 = LCELL( _EQ063);
  _EQ063 = !_LC2_H19 & !_LC4_H36 & !_LC5_H19
         #  _LC1_H19 & !_LC4_H36 &  _LC5_H19
         #  _LC1_H19 & !_LC2_H19 & !_LC4_H36
         #  _LC2_H19 & !_LC4_H36 &  _LC5_H19;

-- Node name is '|scanner:20|:218' 
-- Equation name is '_LC6_H36', type is buried 
_LC6_H36 = LCELL( _EQ064);
  _EQ064 =  _LC5_H36 &  _LC6_H36
         #  _LC1_H36;

-- Node name is ':8' 
-- Equation name is '_LC8_H26', type is buried 
_LC8_H26 = DFFE( _LC1_H26, GLOBAL( clk),  clrN,  prN,  VCC);

-- Node name is ':9' 
-- Equation name is '_LC2_H26', type is buried 
_LC2_H26 = DFFE( _LC8_H26, GLOBAL( clk),  clrN,  prN,  VCC);

-- Node name is ':18' 
-- Equation name is '_LC1_H26', type is buried 
_LC1_H26 = LCELL( _EQ065);
  _EQ065 =  _LC4_H26 &  row1 &  row2;



Project Information                        c:\maxplus2\verilog8\keyscanner.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 55,258K