📄 keyscanner.rpt
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Total flipflops required: 9
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 44/4992 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 EA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
G: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
H: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 8 3 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 8 8 8 8 0 0 67/0
I: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
J: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
K: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
L: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 8 3 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 8 8 8 8 0 0 67/0
Device-Specific Information: c:\maxplus2\verilog8\keyscanner.rpt
keyscanner
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
H11 - - - -- INPUT G ^ 0 0 0 0 clk
Y7 - - - 12 INPUT ^ 0 0 0 2 clrN
Y6 - - - 08 INPUT ^ 0 0 0 2 prN
Y11 - - - 25 INPUT ^ 0 0 0 3 row0
U11 - - - 24 INPUT ^ 0 0 0 5 row1
Y10 - - - 21 INPUT ^ 0 0 0 5 row2
W10 - - - 22 INPUT ^ 0 0 0 3 row3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\maxplus2\verilog8\keyscanner.rpt
keyscanner
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
AA9 - - - 18 OUTPUT 0 1 0 0 c0
AB9 - - - 19 OUTPUT 0 1 0 0 c1
U10 - - - 20 OUTPUT 0 1 0 0 c2
V10 - - - 20 OUTPUT 0 1 0 0 c3
W18 - - - 47 OUTPUT 0 1 0 0 n0
Y19 - - - 50 OUTPUT 0 1 0 0 n1
Y18 - - - 49 OUTPUT 0 1 0 0 n2
AA18 - - - 48 OUTPUT 0 1 0 0 n3
Y14 - - - 35 OUTPUT 0 1 0 0 v
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\maxplus2\verilog8\keyscanner.rpt
keyscanner
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - H 17 AND2 s ! 0 4 0 2 |decoder:26|~14~1
- 3 - H 47 AND2 s ! 0 3 0 2 |decoder:26|~40~1
- 3 - H 17 OR2 s ! 0 4 0 4 |decoder:26|~53~1
- 6 - H 26 AND2 s 4 0 0 4 |decoder:26|~53~2
- 4 - H 50 OR2 s 0 2 0 2 |decoder:26|~79~1
- 4 - H 49 AND2 s ! 0 4 0 2 |decoder:26|~92~1
- 3 - H 26 AND2 s 2 0 0 5 |decoder:26|~105~1
- 5 - H 49 OR2 s ! 0 2 0 3 |decoder:26|~105~2
- 7 - H 26 AND2 s ! 2 0 0 8 |decoder:26|~118~1
- 2 - H 20 AND2 s ! 0 2 0 3 |decoder:26|~118~2
- 1 - H 47 OR2 ! 0 4 0 1 |decoder:26|:118
- 1 - H 50 OR2 ! 0 4 0 2 |decoder:26|:131
- 2 - H 49 AND2 s 0 2 0 4 |decoder:26|~144~1
- 4 - H 26 AND2 s 2 0 0 5 |decoder:26|~157~1
- 5 - H 48 AND2 s 0 2 0 1 |decoder:26|~157~2
- 5 - H 26 AND2 s 4 0 0 5 |decoder:26|~170~1
- 6 - H 49 AND2 s 0 3 0 5 |decoder:26|~196~1
- 3 - H 48 OR2 s 0 3 0 1 |decoder:26|~236~1
- 5 - H 17 OR2 s ! 0 4 0 2 |decoder:26|~236~2
- 1 - H 49 OR2 s 0 4 0 1 |decoder:26|~236~3
- 6 - H 50 AND2 s 0 2 0 1 |decoder:26|~236~4
- 3 - H 50 OR2 s 0 4 0 2 |decoder:26|~236~5
- 6 - H 48 OR2 s 0 4 0 1 |decoder:26|~242~1
- 7 - H 48 OR2 s 0 4 0 1 |decoder:26|~242~2
- 8 - H 48 OR2 s 0 4 0 1 |decoder:26|~242~3
- 5 - H 50 OR2 s ! 0 4 0 2 |decoder:26|~245~1
- 7 - H 49 OR2 s 0 4 0 2 |decoder:26|~245~2
- 1 - H 48 OR2 s 0 4 0 2 |decoder:26|~245~3
- 7 - H 50 OR2 s 0 4 0 1 |decoder:26|~245~4
- 8 - H 50 OR2 s 0 4 0 1 |decoder:26|~245~5
- 2 - H 47 OR2 s 0 4 0 1 |decoder:26|~248~1
- 8 - H 17 OR2 s 0 3 0 1 |decoder:26|~248~2
- 4 - H 17 OR2 s 0 4 0 1 |decoder:26|~248~3
- 3 - H 49 OR2 s ! 0 4 0 2 |decoder:26|~248~4
- 6 - H 47 OR2 s 0 4 0 1 |decoder:26|~251~1
- 7 - H 47 OR2 s 0 4 0 1 |decoder:26|~251~2
- 8 - H 47 OR2 s 0 4 0 1 |decoder:26|~251~3
- 2 - H 48 DFFE 0 5 1 0 |decoder:26|:254
- 2 - H 50 DFFE 0 5 1 0 |decoder:26|:255
- 8 - H 49 DFFE 0 3 1 0 |decoder:26|:256
- 5 - H 47 DFFE 0 5 1 0 |decoder:26|:257
- 4 - H 48 AND2 s 0 4 0 1 row0~1
- 4 - H 47 AND2 s 0 3 0 1 row1~1
- 8 - H 36 AND2 0 3 0 3 |scanner:20|:38
- 2 - H 17 AND2 0 3 0 1 |scanner:20|:60
- 3 - H 36 AND2 0 3 0 3 |scanner:20|:82
- 1 - H 36 AND2 0 3 0 5 |scanner:20|:111
- 7 - H 19 OR2 0 3 0 2 |scanner:20|:145
- 2 - H 36 AND2 ! 0 2 0 4 |scanner:20|:153
- 4 - H 36 OR2 s ! 0 3 0 3 |scanner:20|~159~1
- 8 - H 19 OR2 s 0 4 0 1 |scanner:20|~159~2
- 7 - H 36 OR2 s 0 4 0 2 |scanner:20|~159~3
- 3 - H 19 OR2 s 0 4 0 1 |scanner:20|~160~1
- 4 - H 19 OR2 s 0 4 0 1 |scanner:20|~160~2
- 5 - H 19 DFFE + 0 4 0 10 |scanner:20|state0 (|scanner:20|:164)
- 1 - H 19 DFFE + 0 4 0 10 |scanner:20|state1 (|scanner:20|:165)
- 2 - H 19 DFFE + 0 4 0 10 |scanner:20|state2 (|scanner:20|:166)
- 1 - H 17 OR2 s 0 3 0 2 |scanner:20|~201~1
- 6 - H 17 OR2 0 3 1 11 |scanner:20|:201
- 4 - H 20 OR2 0 3 1 12 |scanner:20|:202
- 8 - H 20 OR2 0 3 1 15 |scanner:20|:203
- 6 - H 19 OR2 0 3 1 10 |scanner:20|:204
- 5 - H 36 OR2 s 0 4 0 3 |scanner:20|~217~1
- 6 - H 36 OR2 0 2 1 4 |scanner:20|:218
- 8 - H 26 DFFE + 2 1 0 1 :8
- 2 - H 26 DFFE + 2 1 0 4 :9
- 1 - H 26 AND2 2 1 0 5 :18
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: c:\maxplus2\verilog8\keyscanner.rpt
keyscanner
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 30/208( 14%) 7/104( 6%) 9/104( 8%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
I: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
J: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
K: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
L: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
25: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
37: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
38: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
39: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
40: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
41: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
42: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
43: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
44: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
45: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
46: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
47: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
48: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
49: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
50: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
51: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
52: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\maxplus2\verilog8\keyscanner.rpt
keyscanner
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 6 |scanner:20|:218
INPUT 5 clk
Device-Specific Information: c:\maxplus2\verilog8\keyscanner.rpt
keyscanner
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 2 clrN
Device-Specific Information: c:\maxplus2\verilog8\keyscanner.rpt
keyscanner
** EQUATIONS **
clk : INPUT;
clrN : INPUT;
prN : INPUT;
row0 : INPUT;
row1 : INPUT;
row2 : INPUT;
row3 : INPUT;
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