scanner.v

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module scanner(kd,k,col,clk,v);
input kd,k,clk;
output [0:3] col;
output v;
reg [0:2] state,n_state;
reg [0:3] col;
reg v;
parameter s0=3'b000,s1=3'b001,s2=3'b010,s3=3'b011,s4=3'b100,s5=3'b101,s6=3'b110;

always@(posedge clk)
state<=n_state;

always 
begin
case(state)
s0: n_state=s1;
s1: begin
       v=1'b0;
       col=4'b0000;
       n_state=(kd==1)?s1:s2;
    end
s2: begin
       v=1'b0;
       col=4'b0111;
       n_state=(k==1)?s3:s6;
    end
s3: begin
       v=1'b0;
       col=4'b1011;
       n_state=(k==1)?s4:s6;
    end
s4: begin
       v=1'b0;
       col=4'b1101;
       n_state=(k==1)?s5:s6;
    end
s5: begin
       v=1'b0;
       col=4'b1110;
       n_state=s6;
    end
s6: begin
       v=1'b1;
       col=4'b0000;
       n_state=(k==0)?s6:(kd==0)?s6:s1;
    end
default: n_state=s1;
endcase
end
endmodule