📄 simpe_alu.rpt
字号:
- 6 - E 04 OR2 s 2 2 0 1 |alu:1|~166~2
- 7 - E 04 OR2 s 0 4 0 1 |alu:1|~166~3
- 1 - E 04 OR2 0 4 0 2 |alu:1|:166
- 5 - E 20 OR2 s 2 2 0 1 |alu:1|~170~1
- 6 - E 20 OR2 s 2 2 0 1 |alu:1|~170~2
- 7 - E 20 OR2 s 1 3 0 1 |alu:1|~170~3
- 8 - E 20 OR2 s 1 3 0 1 |alu:1|~170~4
- 2 - E 20 OR2 0 4 0 3 |alu:1|:170
- 3 - E 03 OR2 2 2 0 1 |alu:1|:194
- 4 - E 08 OR2 2 2 0 1 |alu:1|:195
- 4 - E 05 OR2 2 2 0 1 |alu:1|:198
- 8 - E 21 OR2 2 2 0 1 |alu:1|:199
- 3 - E 08 OR2 2 2 0 1 |alu:1|:203
- 3 - E 05 OR2 2 2 0 1 |alu:1|:206
- 7 - E 03 OR2 2 2 0 1 |alu:1|:226
- 6 - E 05 OR2 3 1 0 1 |alu:1|:230
- 4 - E 03 OR2 1 2 0 1 |alu:1|:234
- 5 - E 03 OR2 s 2 2 0 1 |alu:1|~258~1
- 6 - E 03 OR2 s 2 2 0 1 |alu:1|~258~2
- 8 - E 03 OR2 s 0 4 0 1 |alu:1|~258~3
- 2 - E 03 OR2 0 4 0 3 |alu:1|:258
- 5 - E 08 OR2 s 2 2 0 1 |alu:1|~259~1
- 6 - E 08 OR2 s 1 3 0 1 |alu:1|~259~2
- 7 - E 08 OR2 s 1 3 0 1 |alu:1|~259~3
- 8 - E 08 OR2 s 2 2 0 1 |alu:1|~259~4
- 2 - E 08 OR2 0 4 0 3 |alu:1|:259
- 2 - E 05 OR2 s 2 2 0 1 |alu:1|~262~1
- 7 - E 05 OR2 s 2 2 0 1 |alu:1|~262~2
- 8 - E 05 OR2 s 0 4 0 1 |alu:1|~262~3
- 1 - E 05 OR2 0 4 0 3 |alu:1|:262
- 7 - E 23 OR2 s 2 2 0 1 |alu:1|~263~1
- 1 - E 23 OR2 s 1 3 0 1 |alu:1|~263~2
- 7 - E 11 OR2 s 2 2 0 1 |alu:1|~263~3
- 2 - E 23 OR2 s 2 2 0 1 |alu:1|~263~4
- 1 - E 21 OR2 0 4 0 3 |alu:1|:263
- 3 - E 21 OR2 s 0 2 0 1 |alu:1|~264~1
- 4 - E 21 OR2 s 2 2 0 1 |alu:1|~264~2
- 6 - E 21 OR2 s 1 3 0 1 |alu:1|~264~3
- 7 - E 21 OR2 s 1 2 0 1 |alu:1|~264~4
- 2 - E 21 OR2 0 4 0 2 |alu:1|:264
- 7 - E 18 OR2 2 2 0 1 |alu:1|:287
- 6 - E 18 OR2 2 2 0 1 |alu:1|:295
- 7 - E 12 OR2 s 2 2 0 1 |alu:1|~351~1
- 8 - E 12 OR2 s 1 3 0 1 |alu:1|~351~2
- 4 - E 12 OR2 s 1 3 0 1 |alu:1|~351~3
- 8 - E 23 OR2 s 2 2 0 1 |alu:1|~351~4
- 3 - E 23 OR2 0 4 0 3 |alu:1|:351
- 5 - E 19 OR2 s 2 2 0 1 |alu:1|~376~1
- 2 - E 24 OR2 s 2 2 0 1 |alu:1|~377~1
- 3 - E 24 OR2 s 2 2 0 1 |alu:1|~378~1
- 4 - E 24 OR2 s 2 2 0 1 |alu:1|~379~1
- 7 - E 19 OR2 s 2 2 0 1 |alu:1|~380~1
- 3 - E 19 OR2 s 2 2 0 1 |alu:1|~381~1
- 8 - E 24 DFFE + 2 2 0 1 |alu:1|:383
- 6 - E 19 DFFE + 2 2 0 1 |alu:1|:384
- 6 - E 24 DFFE + 2 2 0 1 |alu:1|:385
- 5 - E 24 DFFE + 2 2 0 1 |alu:1|:386
- 7 - E 24 DFFE + 2 2 0 1 |alu:1|:387
- 8 - E 19 DFFE + 2 2 0 1 |alu:1|:388
- 2 - E 19 DFFE + 2 2 0 1 |alu:1|:389
- 4 - E 19 DFFE + 2 2 0 1 |alu:1|:390
- 4 - E 36 AND2 ! 2 1 1 0 |alu:1|:392
- 8 - K 13 AND2 0 4 0 2 |btoseven:2|:39
- 4 - K 17 AND2 s 0 2 0 4 |btoseven:2|~65~1
- 3 - K 17 AND2 s 0 2 0 3 |btoseven:2|~65~2
- 1 - K 17 AND2 0 3 0 1 |btoseven:2|:117
- 7 - K 17 AND2 0 4 0 1 |btoseven:2|:130
- 1 - K 18 AND2 0 4 0 3 |btoseven:2|:195
- 2 - K 13 OR2 s 0 4 0 2 |btoseven:2|~248~1
- 4 - K 10 OR2 0 4 1 0 |btoseven:2|:248
- 2 - K 17 OR2 0 4 1 0 |btoseven:2|:251
- 3 - K 18 AND2 s 0 2 0 3 |btoseven:2|~254~1
- 6 - K 18 OR2 s 0 2 0 1 |btoseven:2|~254~2
- 4 - K 13 OR2 0 4 1 0 |btoseven:2|:254
- 5 - K 13 OR2 s 0 4 0 2 |btoseven:2|~257~1
- 6 - K 13 OR2 s 0 4 0 2 |btoseven:2|~257~2
- 1 - K 15 OR2 0 4 1 0 |btoseven:2|:257
- 5 - K 18 OR2 s 0 4 0 2 |btoseven:2|~260~1
- 2 - K 16 OR2 0 3 1 0 |btoseven:2|:260
- 4 - K 18 OR2 s 0 4 0 2 |btoseven:2|~263~1
- 3 - K 13 OR2 s 0 4 0 2 |btoseven:2|~263~2
- 1 - K 13 OR2 0 4 1 0 |btoseven:2|:263
- 7 - K 13 OR2 s 0 2 0 2 |btoseven:2|~266~1
- 7 - K 18 OR2 s 0 4 0 1 |btoseven:2|~266~2
- 8 - K 18 OR2 s 0 3 0 1 |btoseven:2|~266~3
- 2 - K 18 OR2 0 4 1 0 |btoseven:2|:266
- 2 - B 20 LCELL s 1 0 1 0 ds0~1
- 1 - H 20 LCELL s 1 0 1 0 ds1~1
- 1 - E 24 OR2 ! 1 2 0 12 |for4bitmux2:3|:28
- 1 - E 19 OR2 1 2 0 13 |for4bitmux2:3|:29
- 6 - K 17 OR2 ! 1 2 0 12 |for4bitmux2:3|:30
- 5 - K 17 OR2 1 2 0 12 |for4bitmux2:3|:31
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: c:\maxplus2\verilog7\simpe_alu.rpt
simpe_alu
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 14/208( 6%) 45/104( 43%) 1/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
I: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
J: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
K: 0/208( 0%) 20/104( 19%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
L: 1/208( 0%) 0/104( 0%) 0/104( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
08: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
19: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
37: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
38: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
39: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
40: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
41: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
42: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
43: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
44: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
45: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
46: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
47: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
48: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
49: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
50: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
51: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
52: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\maxplus2\verilog7\simpe_alu.rpt
simpe_alu
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 14 clock
Device-Specific Information: c:\maxplus2\verilog7\simpe_alu.rpt
simpe_alu
** EQUATIONS **
accum0 : INPUT;
accum1 : INPUT;
accum2 : INPUT;
accum3 : INPUT;
accum4 : INPUT;
accum5 : INPUT;
accum6 : INPUT;
accum7 : INPUT;
clock : INPUT;
data0 : INPUT;
data1 : INPUT;
data2 : INPUT;
data3 : INPUT;
data4 : INPUT;
data5 : INPUT;
data6 : INPUT;
data7 : INPUT;
opcode0 : INPUT;
opcode1 : INPUT;
opcode2 : INPUT;
opcode3 : INPUT;
opcode4 : INPUT;
-- Node name is 'ds0~1'
-- Equation name is 'ds0~1', location is LC2_B20, type is buried.
-- synthesized logic cell
_LC2_B20 = LCELL( clock);
-- Node name is 'ds0'
-- Equation name is 'ds0', type is output
ds0 = !_LC2_B20;
-- Node name is 'ds1~1'
-- Equation name is 'ds1~1', location is LC1_H20, type is buried.
-- synthesized logic cell
_LC1_H20 = LCELL( clock);
-- Node name is 'ds1'
-- Equation name is 'ds1', type is output
ds1 = _LC1_H20;
-- Node name is 'ds2'
-- Equation name is 'ds2', type is output
ds2 = GND;
-- Node name is 'ds3'
-- Equation name is 'ds3', type is output
ds3 = GND;
-- Node name is 'sout0'
-- Equation name is 'sout0', type is output
sout0 = _LC2_K18;
-- Node name is 'sout1'
-- Equation name is 'sout1', type is output
sout1 = _LC1_K13;
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