📄 simpe_alu.rpt
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D4 ^DATA0 H13 RESERVED M22 RESERVED U9 sout4 AA18 opcode4
D5 RESERVED H14 VCCINT N1 N.C. U10 ds1 AA19 RESERVED
D6 GND H15 GND N2 RESERVED U11 RESERVED AA20 opcode0
D7 RESERVED H16 RESERVED N3 VCCIO U12 RESERVED AA21 RESERVED
D8 RESERVED H17 RESERVED N4 RESERVED U13 RESERVED AA22 GND
D9 RESERVED H18 RESERVED N5 RESERVED U14 RESERVED AB1 accum6
D10 RESERVED H19 RESERVED N6 RESERVED U15 RESERVED AB2 RESERVED
D11 RESERVED H20 VCCIO N7 RESERVED U16 RESERVED AB3 N.C.
D12 GND H21 RESERVED N8 GND U17 RESERVED AB4 N.C.
D13 RESERVED H22 RESERVED N9 VCCIO U18 #TMS AB5 N.C.
D14 RESERVED J1 RESERVED N10 GND U19 RESERVED AB6 data6
D15 RESERVED J2 N.C. N11 VCCIO U20 RESERVED AB7 N.C.
D16 RESERVED J3 RESERVED N12 VCCINT U21 RESERVED AB8 sout3
D17 GND J4 RESERVED N13 GND U22 RESERVED AB9 ds2
D18 RESERVED J5 RESERVED N14 VCCIO V1 RESERVED AB10 RESERVED
D19 RESERVED J6 RESERVED N15 RESERVED V2 RESERVED AB11 GND
D20 RESERVED J7 RESERVED N16 RESERVED V3 GND AB12 RESERVED
D21 RESERVED J8 VCCINT N17 RESERVED V4 ^MSEL1 AB13 VCCIO
D22 RESERVED J9 GND N18 RESERVED V5 VCCINT AB14 RESERVED
E1 VCCIO J10 VCCINT N19 RESERVED V6 accum7 AB15 N.C.
E2 RESERVED J11 VCCIO N20 VCCIO V7 data4 AB16 GND
E3 RESERVED J12 VCCINT N21 RESERVED V8 sout6 AB17 N.C.
E4 ^nCE J13 VCCIO N22 RESERVED V9 sout7 AB18 N.C.
E5 ^DCLK J14 GND P1 RESERVED V10 ds0 AB19 N.C.
E6 RESERVED J15 VCCINT P2 RESERVED V11 GND AB20 N.C.
E7 RESERVED J16 RESERVED P3 RESERVED V12 RESERVED AB21 RESERVED
E8 RESERVED J17 RESERVED P4 GND V13 RESERVED AB22 RESERVED
E9 RESERVED J18 RESERVED P5 RESERVED V14 RESERVED
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: c:\maxplus2\verilog7\simpe_alu.rpt
simpe_alu
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
B20 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/26( 3%)
E1 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 3/26( 11%)
E3 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 15/26( 57%)
E4 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 16/26( 61%)
E5 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 14/26( 53%)
E8 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 14/26( 53%)
E11 5/ 8( 62%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 8/26( 30%)
E12 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 11/26( 42%)
E18 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 13/26( 50%)
E19 8/ 8(100%) 3/ 8( 37%) 0/ 8( 0%) 1/2 0/2 10/26( 38%)
E20 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 14/26( 53%)
E21 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 15/26( 57%)
E23 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 14/26( 53%)
E24 8/ 8(100%) 3/ 8( 37%) 0/ 8( 0%) 1/2 0/2 9/26( 34%)
E36 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/26( 11%)
H20 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/26( 3%)
K10 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/26( 15%)
K13 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 0/2 0/2 5/26( 19%)
K15 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/26( 15%)
K16 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/26( 11%)
K17 7/ 8( 87%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 10/26( 38%)
K18 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 9/26( 34%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 34/327 ( 10%)
Total logic cells used: 130/4992 ( 2%)
Total embedded cells used: 0/192 ( 0%)
Total EABs used: 0/12 ( 0%)
Average fan-in: 3.54/4 ( 88%)
Total fan-in: 461/19968 ( 2%)
Total input pins required: 22
Total input I/O cell registers required: 0
Total output pins required: 13
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 130
Total flipflops required: 8
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 51/4992 ( 1%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 EA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 8 0 8 8 8 0 0 8 0 0 5 8 0 0 0 0 0 8 8 8 8 0 8 8 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 102/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
G: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
H: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1/0
I: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
J: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
K: 0 0 0 0 0 0 0 0 0 1 0 0 8 0 1 1 7 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26/0
L: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 8 0 8 8 8 0 0 8 0 1 5 8 8 0 1 1 7 16 8 10 8 0 8 8 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 130/0
Device-Specific Information: c:\maxplus2\verilog7\simpe_alu.rpt
simpe_alu
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
W6 - - - 06 INPUT ^ 0 0 0 13 accum0
W5 - - - 02 INPUT ^ 0 0 0 13 accum1
AA5 - - - 07 INPUT ^ 0 0 0 12 accum2
Y5 - - - 03 INPUT ^ 0 0 0 10 accum3
AA2 - - - 01 INPUT ^ 0 0 0 10 accum4
U7 - - - 03 INPUT ^ 0 0 0 11 accum5
AB1 - - - 05 INPUT ^ 0 0 0 11 accum6
V6 - - L -- INPUT ^ 0 0 0 7 accum7
H11 - - - -- INPUT G ^ 0 0 0 6 clock
Y7 - - - 12 INPUT ^ 0 0 0 6 data0
AA7 - - - 12 INPUT ^ 0 0 0 6 data1
W7 - - - 10 INPUT ^ 0 0 0 6 data2
U8 - - - 08 INPUT ^ 0 0 0 6 data3
V7 - - - 07 INPUT ^ 0 0 0 6 data4
Y4 - - - 02 INPUT ^ 0 0 0 6 data5
AB6 - - - 11 INPUT ^ 0 0 0 6 data6
Y6 - - - 08 INPUT ^ 0 0 0 4 data7
AA20 - - - 51 INPUT ^ 0 0 0 14 opcode0
W18 - - - 47 INPUT ^ 0 0 0 14 opcode1
Y19 - - - 50 INPUT ^ 0 0 0 8 opcode2
Y18 - - - 49 INPUT ^ 0 0 0 8 opcode3
AA18 - - - 48 INPUT ^ 0 0 0 8 opcode4
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\maxplus2\verilog7\simpe_alu.rpt
simpe_alu
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
V10 - - - 20 OUTPUT 0 1 0 0 ds0
U10 - - - 20 OUTPUT 0 1 0 0 ds1
AB9 - - - 19 OUTPUT 0 0 0 0 ds2
AA9 - - - 18 OUTPUT 0 0 0 0 ds3
W9 - - - 18 OUTPUT 0 1 0 0 sout0
W8 - - - 13 OUTPUT 0 1 0 0 sout1
AA8 - - - 15 OUTPUT 0 1 0 0 sout2
AB8 - - - 15 OUTPUT 0 1 0 0 sout3
U9 - - - 14 OUTPUT 0 1 0 0 sout4
Y9 - - - 17 OUTPUT 0 1 0 0 sout5
V8 - - - 09 OUTPUT 0 1 0 0 sout6
V9 - - - 14 OUTPUT 0 0 0 0 sout7
Y14 - - - 35 OUTPUT 0 1 0 0 zero
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\maxplus2\verilog7\simpe_alu.rpt
simpe_alu
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - E 23 OR2 4 0 0 2 |alu:1|lpm_add_sub:394|addcore:adder|pcarry1
- 3 - E 11 OR2 2 1 0 2 |alu:1|lpm_add_sub:394|addcore:adder|pcarry2
- 8 - E 18 OR2 2 1 0 2 |alu:1|lpm_add_sub:394|addcore:adder|pcarry3
- 4 - E 18 OR2 2 1 0 2 |alu:1|lpm_add_sub:394|addcore:adder|pcarry4
- 1 - E 18 OR2 2 1 0 2 |alu:1|lpm_add_sub:394|addcore:adder|pcarry5
- 2 - E 18 OR2 2 1 0 1 |alu:1|lpm_add_sub:394|addcore:adder|pcarry6
- 5 - E 21 AND2 2 0 0 2 |alu:1|lpm_add_sub:394|addcore:adder|:114
- 4 - E 23 OR2 4 0 0 2 |alu:1|lpm_add_sub:395|addcore:adder|pcarry1
- 2 - E 11 OR2 2 1 0 2 |alu:1|lpm_add_sub:395|addcore:adder|pcarry2
- 1 - E 20 OR2 2 1 0 2 |alu:1|lpm_add_sub:395|addcore:adder|pcarry3
- 5 - E 18 OR2 2 1 0 2 |alu:1|lpm_add_sub:395|addcore:adder|pcarry4
- 1 - E 08 OR2 2 1 0 2 |alu:1|lpm_add_sub:395|addcore:adder|pcarry5
- 3 - E 18 OR2 2 1 0 1 |alu:1|lpm_add_sub:395|addcore:adder|pcarry6
- 6 - E 23 OR2 s 3 0 0 1 |alu:1|lpm_add_sub:395|addcore:adder|~156~1
- 1 - E 03 OR2 2 1 0 1 |alu:1|lpm_add_sub:395|addcore:adder|:161
- 4 - E 11 AND2 3 0 0 1 |alu:1|lpm_add_sub:396|addcore:adder|:125
- 6 - E 12 AND2 4 0 0 2 |alu:1|lpm_add_sub:396|addcore:adder|:129
- 2 - E 12 AND2 1 1 0 3 |alu:1|lpm_add_sub:396|addcore:adder|:133
- 4 - E 04 OR2 3 1 0 1 |alu:1|lpm_add_sub:396|addcore:adder|:155
- 1 - E 11 OR2 3 0 0 1 |alu:1|lpm_add_sub:397|addcore:adder|pcarry2
- 5 - E 12 AND2 ! 4 0 0 2 |alu:1|lpm_add_sub:397|addcore:adder|pcarry3
- 3 - E 12 AND2 ! 1 1 0 2 |alu:1|lpm_add_sub:397|addcore:adder|pcarry4
- 1 - E 12 AND2 ! 1 1 0 3 |alu:1|lpm_add_sub:397|addcore:adder|pcarry5
- 5 - E 05 OR2 3 0 0 1 |alu:1|lpm_add_sub:397|addcore:adder|:150
- 6 - E 01 AND2 3 0 0 8 |alu:1|:36
- 3 - E 01 AND2 3 0 0 8 |alu:1|:48
- 3 - E 04 OR2 2 2 0 1 |alu:1|:52
- 4 - E 20 OR2 2 2 0 1 |alu:1|:56
- 4 - E 01 AND2 3 0 0 8 |alu:1|:60
- 2 - E 04 OR2 2 2 0 1 |alu:1|:65
- 3 - E 20 OR2 2 2 0 1 |alu:1|:69
- 5 - E 01 AND2 3 0 0 8 |alu:1|:73
- 2 - E 01 AND2 3 0 0 8 |alu:1|:93
- 1 - E 01 AND2 3 0 0 8 |alu:1|:113
- 8 - E 01 AND2 3 0 0 8 |alu:1|:125
- 8 - E 04 OR2 2 2 0 1 |alu:1|:130
- 7 - E 01 AND2 3 0 0 8 |alu:1|:138
- 5 - E 04 OR2 s 2 2 0 1 |alu:1|~166~1
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