📄 simpe_alu.rpt
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Project Information c:\maxplus2\verilog7\simpe_alu.rpt
MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 05/02/2007 03:06:37
Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
simpe_alu
EP1K100FC484-3 22 13 0 0 0 % 130 2 %
User Pins: 22 13 0
Project Information c:\maxplus2\verilog7\simpe_alu.rpt
** PROJECT TIMING MESSAGES **
Warning: Timing characteristics of device EP1K100FC484-3 are preliminary
Project Information c:\maxplus2\verilog7\simpe_alu.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
simpe_alu@W6 accum0
simpe_alu@W5 accum1
simpe_alu@AA5 accum2
simpe_alu@Y5 accum3
simpe_alu@AA2 accum4
simpe_alu@U7 accum5
simpe_alu@AB1 accum6
simpe_alu@V6 accum7
simpe_alu@H11 clock
simpe_alu@Y7 data0
simpe_alu@AA7 data1
simpe_alu@W7 data2
simpe_alu@U8 data3
simpe_alu@V7 data4
simpe_alu@Y4 data5
simpe_alu@AB6 data6
simpe_alu@Y6 data7
simpe_alu@V10 ds0
simpe_alu@U10 ds1
simpe_alu@AB9 ds2
simpe_alu@AA9 ds3
simpe_alu@AA20 opcode0
simpe_alu@W18 opcode1
simpe_alu@Y19 opcode2
simpe_alu@Y18 opcode3
simpe_alu@AA18 opcode4
simpe_alu@W9 sout0
simpe_alu@W8 sout1
simpe_alu@AA8 sout2
simpe_alu@AB8 sout3
simpe_alu@U9 sout4
simpe_alu@Y9 sout5
simpe_alu@V8 sout6
simpe_alu@V9 sout7
simpe_alu@Y14 zero
Project Information c:\maxplus2\verilog7\simpe_alu.rpt
** FILE HIERARCHY **
|alu:1|
|alu:1|lpm_add_sub:394|
|alu:1|lpm_add_sub:394|addcore:adder|
|alu:1|lpm_add_sub:394|altshift:result_ext_latency_ffs|
|alu:1|lpm_add_sub:394|altshift:carry_ext_latency_ffs|
|alu:1|lpm_add_sub:394|altshift:oflow_ext_latency_ffs|
|alu:1|lpm_add_sub:395|
|alu:1|lpm_add_sub:395|addcore:adder|
|alu:1|lpm_add_sub:395|altshift:result_ext_latency_ffs|
|alu:1|lpm_add_sub:395|altshift:carry_ext_latency_ffs|
|alu:1|lpm_add_sub:395|altshift:oflow_ext_latency_ffs|
|alu:1|lpm_add_sub:396|
|alu:1|lpm_add_sub:396|addcore:adder|
|alu:1|lpm_add_sub:396|altshift:result_ext_latency_ffs|
|alu:1|lpm_add_sub:396|altshift:carry_ext_latency_ffs|
|alu:1|lpm_add_sub:396|altshift:oflow_ext_latency_ffs|
|alu:1|lpm_add_sub:397|
|alu:1|lpm_add_sub:397|addcore:adder|
|alu:1|lpm_add_sub:397|altshift:result_ext_latency_ffs|
|alu:1|lpm_add_sub:397|altshift:carry_ext_latency_ffs|
|alu:1|lpm_add_sub:397|altshift:oflow_ext_latency_ffs|
|btoseven:2|
|for4bitmux2:3|
Device-Specific Information: c:\maxplus2\verilog7\simpe_alu.rpt
simpe_alu
***** Logic for device 'simpe_alu' compiled without errors.
Device: EP1K100FC484-3
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
----------------------------------------------------------------------
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 |
|AB o o o o o o o o o o o o o o o o o o o o o o AB|
|AA o o o o o o o o o o o o o o o o o o o o o o AA|
|Y o o o o o o o o o o o o o o o o o o o o o o Y|
|W o o o o o o o o o o o o o o o o o o o o o o W|
|V o o o o o o o o o o o o o o o o o o o o o o V|
|U o o o o o o o o o o o o o o o o o o o o o o U|
|T o o o o o o o o o o o o o o o o o o o o o o T|
|R o o o o o o o o o o o o o o o o o o o o o o R|
|P o o o o o o o o o o o o o o o o o o o o o o P|
|N o o o o o o o o o o o o o o o o o o o o o o N|
|M o o o o o o o o o o o o o o o o o o o o o o M|
|L o o o o o o o o o o o o o o o o o o o o o o L|
|K o o o o o o o o o o o o o o o o o o o o o o K|
|J o o o o o o o o o o o o o o o o o o o o o o J|
|H o o o o o o o o o o o o o o o o o o o o o o H|
|G o o o o o o o o o o o o o o o o o o o o o o G|
|F o o o o o o o o o o o o o o o o o o o o o o F|
|E o o o o o o o o o o o o o o o o o o o o o o E|
|D o o o o o o o o o o o o o o o o o o o o o o D|
|C o o o o o o o o o o o o o o o o o o o o o o C|
|B o o o o o o o o o o o o o o o o o o o o o o B|
|A o o o o o o o o o o o o o o o o o o o o o o A|
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 |
----------------------------------------------------------------------
EP1K100FC484-3
Bottom View
Device-Specific Information: c:\maxplus2\verilog7\simpe_alu.rpt
simpe_alu
A1 GND E10 RESERVED J19 RESERVED P6 RESERVED V15 RESERVED
A2 N.C. E11 RESERVED J20 GND P7 RESERVED V16 RESERVED
A3 N.C. E12 GND J21 RESERVED P8 VCCINT V17 RESERVED
A4 N.C. E13 RESERVED J22 RESERVED P9 GND V18 RESERVED
A5 N.C. E14 RESERVED K1 RESERVED P10 VCCINT V19 #TRST
A6 VCCIO E15 RESERVED K2 N.C. P11 GND V20 RESERVED
A7 RESERVED E16 RESERVED K3 GND P12 VCCINT V21 RESERVED
A8 GND E17 RESERVED K4 RESERVED P13 VCCIO V22 VCCIO
A9 RESERVED E18 #TCK K5 RESERVED P14 GND W1 RESERVED
A10 RESERVED E19 ^nCEO K6 RESERVED P15 VCCINT W2 RESERVED
A11 RESERVED E20 RESERVED K7 RESERVED P16 RESERVED W3 RESERVED
A12 RESERVED E21 GND K8 RESERVED P17 RESERVED W4 RESERVED
A13 VCCIO E22 RESERVED K9 VCCIO P18 RESERVED W5 accum1
A14 RESERVED F1 RESERVED K10 GND P19 RESERVED W6 accum0
A15 RESERVED F2 N.C. K11 VCCIO P20 N.C. W7 data2
A16 RESERVED F3 RESERVED K12 GND P21 RESERVED W8 sout1
A17 RESERVED F4 RESERVED K13 GND P22 N.C. W9 sout0
A18 RESERVED F5 #TDI K14 VCCIO R1 VCCIO W10 RESERVED
A19 RESERVED F6 RESERVED K15 RESERVED R2 RESERVED W11 GND
A20 RESERVED F7 RESERVED K16 RESERVED R3 N.C. W12 RESERVED
A21 RESERVED F8 RESERVED K17 RESERVED R4 RESERVED W13 RESERVED
A22 GND F9 RESERVED K18 RESERVED R5 RESERVED W14 RESERVED
B1 GND F10 GND K19 RESERVED R6 RESERVED W15 RESERVED
B2 GND F11 RESERVED K20 VCCIO R7 RESERVED W16 RESERVED
B3 N.C. F12 RESERVED K21 RESERVED R8 GND W17 RESERVED
B4 N.C. F13 RESERVED K22 RESERVED R9 VCCIO W18 opcode1
B5 VCCIO F14 RESERVED L1 RESERVED R10 RESERVED W19 ^nSTATUS
B6 RESERVED F15 RESERVED L2 N.C. R11 RESERVED W20 GND
B7 RESERVED F16 RESERVED L3 RESERVED R12 GND W21 VCCINT
B8 RESERVED F17 RESERVED L4 RESERVED R13 RESERVED W22 N.C.
B9 RESERVED F18 ^CONF_DONE L5 RESERVED R14 VCCINT Y1 GND
B10 N.C. F19 #TDO L6 RESERVED R15 GND Y2 GND
B11 RESERVED F20 RESERVED L7 RESERVED R16 RESERVED Y3 GND
B12 RESERVED F21 RESERVED L8 RESERVED R17 RESERVED Y4 data5
B13 RESERVED F22 RESERVED L9 VCCINT R18 RESERVED Y5 accum3
B14 RESERVED G1 VCCIO L10 VCCINT R19 RESERVED Y6 data7
B15 RESERVED G2 RESERVED L11 GND R20 RESERVED Y7 data0
B16 RESERVED G3 GND L12 GND R21 RESERVED Y8 VCCINT
B17 GND G4 RESERVED L13 VCCINT R22 GND Y9 sout5
B18 RESERVED G5 RESERVED L14 VCCIO T1 GND Y10 RESERVED
B19 RESERVED G6 RESERVED L15 RESERVED T2 RESERVED Y11 RESERVED
B20 RESERVED G7 RESERVED L16 RESERVED T3 VCCIO Y12 RESERVED
B21 GND G8 RESERVED L17 RESERVED T4 RESERVED Y13 RESERVED
B22 GND G9 RESERVED L18 RESERVED T5 RESERVED Y14 zero
C1 RESERVED G10 RESERVED L19 RESERVED T6 RESERVED Y15 RESERVED
C2 GND G11 RESERVED L20 RESERVED T7 ^nCONFIG Y16 N.C.
C3 RESERVED G12 RESERVED L21 RESERVED T8 RESERVED Y17 RESERVED
C4 RESERVED G13 RESERVED L22 RESERVED T9 RESERVED Y18 opcode3
C5 RESERVED G14 RESERVED M1 RESERVED T10 RESERVED Y19 opcode2
C6 RESERVED G15 VCCIO M2 RESERVED T11 RESERVED Y20 RESERVED
C7 RESERVED G16 RESERVED M3 RESERVED T12 RESERVED Y21 GND
C8 RESERVED G17 RESERVED M4 RESERVED T13 RESERVED Y22 GND
C9 RESERVED G18 RESERVED M5 RESERVED T14 RESERVED AA1 GND
C10 RESERVED G19 RESERVED M6 RESERVED T15 VCCIO AA2 accum4
C11 VCCINT G20 RESERVED M7 RESERVED T16 RESERVED AA3 RESERVED
C12 RESERVED G21 GND M8 RESERVED T17 RESERVED AA4 RESERVED
C13 RESERVED G22 RESERVED M9 VCCIO T18 RESERVED AA5 accum2
C14 RESERVED H1 RESERVED M10 VCCINT T19 RESERVED AA6 GND
C15 VCCINT H2 GND M11 GND T20 N.C. AA7 data1
C16 RESERVED H3 RESERVED M12 GND T21 N.C. AA8 sout2
C17 N.C. H4 RESERVED M13 VCCINT T22 VCCIO AA9 ds3
C18 RESERVED H5 RESERVED M14 VCCINT U1 N.C. AA10 RESERVED
C19 RESERVED H6 RESERVED M15 RESERVED U2 RESERVED AA11 RESERVED
C20 RESERVED H7 RESERVED M16 RESERVED U3 RESERVED AA12 VCCINT
C21 GND H8 GND M17 RESERVED U4 ^MSEL0 AA13 RESERVED
C22 RESERVED H9 VCCIO M18 RESERVED U5 RESERVED AA14 RESERVED
D1 RESERVED H10 RESERVED M19 RESERVED U6 RESERVED AA15 N.C.
D2 RESERVED H11 clock M20 GND U7 accum5 AA16 RESERVED
D3 RESERVED H12 RESERVED M21 RESERVED U8 data3 AA17 RESERVED
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