alu.v

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module alu(alu_out,zero,opcode,data,accum,clock);
input [7:0] data,accum;
input [4:0] opcode;
input clock;
output [7:0] alu_out;
output zero;
reg zero;
reg [7:0] temp_out,alu_out;
always@(accum)
   zero=(!accum);
always@(negedge clock)
begin
case(opcode[4:2])
3'b000:temp_out = data;
3'b001:temp_out = accum + data;
3'b010:temp_out = accum - data;
3'b011:temp_out = accum & data;
3'b100:temp_out = accum | data;
3'b101:temp_out = accum + 1;
3'b110:temp_out = accum - 1;
3'b111:temp_out = accum;
default:temp_out = 8'b0;
endcase
case(opcode[1:0])
2'b00:alu_out = temp_out;
2'b01:alu_out = {temp_out[6:0],1'b0};
2'b10:alu_out = {1'b0,temp_out[7:1]};
default:alu_out = 8'b0;
endcase
end
endmodule