📄 alu.rpt
字号:
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 25/327 ( 7%)
Total logic cells used: 100/4992 ( 2%)
Total embedded cells used: 0/192 ( 0%)
Total EABs used: 0/12 ( 0%)
Average fan-in: 3.64/4 ( 91%)
Total fan-in: 364/19968 ( 1%)
Total input pins required: 22
Total input I/O cell registers required: 0
Total output pins required: 9
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 100
Total flipflops required: 8
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 35/4992 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 EA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
G: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
H: 0 8 0 8 0 8 0 8 0 0 0 0 8 1 8 0 0 3 8 8 0 8 0 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 100/0
I: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
J: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
K: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
L: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 8 0 8 0 8 0 8 0 0 0 0 8 1 8 0 0 3 8 8 0 8 0 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 100/0
Device-Specific Information: c:\maxplus2\verilog7\alu.rpt
alu
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
R12 - - - -- INPUT ^ 0 0 0 12 accum0
E12 - - - -- INPUT ^ 0 0 0 12 accum1
V11 - - - -- INPUT ^ 0 0 0 11 accum2
E11 - - - 24 INPUT ^ 0 0 0 11 accum3
H11 - - - -- INPUT ^ 0 0 0 12 accum4
P11 - - - -- INPUT ^ 0 0 0 10 accum5
E7 - - - 12 INPUT ^ 0 0 0 11 accum6
E9 - - - 20 INPUT ^ 0 0 0 7 accum7
D12 - - - -- INPUT G ^ 0 0 0 0 clock
W10 - - - 22 INPUT ^ 0 0 0 6 data0
N18 - - H -- INPUT ^ 0 0 0 6 data1
W6 - - - 06 INPUT ^ 0 0 0 6 data2
U8 - - - 08 INPUT ^ 0 0 0 6 data3
Y9 - - - 17 INPUT ^ 0 0 0 6 data4
N22 - - H -- INPUT ^ 0 0 0 6 data5
V9 - - - 14 INPUT ^ 0 0 0 6 data6
AB9 - - - 19 INPUT ^ 0 0 0 4 data7
N21 - - H -- INPUT ^ 0 0 0 14 opcode0
N5 - - H -- INPUT ^ 0 0 0 14 opcode1
G14 - - H -- INPUT ^ 0 0 0 8 opcode2
N7 - - H -- INPUT ^ 0 0 0 8 opcode3
N19 - - H -- INPUT ^ 0 0 0 8 opcode4
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\maxplus2\verilog7\alu.rpt
alu
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
AB21 - - - 50 OUTPUT 0 1 0 0 alu_out0
L15 - - H -- OUTPUT 0 1 0 0 alu_out1
F17 - - - 49 OUTPUT 0 1 0 0 alu_out2
N2 - - H -- OUTPUT 0 1 0 0 alu_out3
U10 - - - 20 OUTPUT 0 1 0 0 alu_out4
P7 - - H -- OUTPUT 0 1 0 0 alu_out5
AA4 - - - 06 OUTPUT 0 1 0 0 alu_out6
N4 - - H -- OUTPUT 0 1 0 0 alu_out7
N6 - - H -- OUTPUT 0 1 0 0 zero
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\maxplus2\verilog7\alu.rpt
alu
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - H 24 OR2 4 0 0 2 |lpm_add_sub:394|addcore:adder|pcarry1
- 7 - H 02 OR2 2 1 0 2 |lpm_add_sub:394|addcore:adder|pcarry2
- 8 - H 02 OR2 2 1 0 2 |lpm_add_sub:394|addcore:adder|pcarry3
- 4 - H 02 OR2 2 1 0 2 |lpm_add_sub:394|addcore:adder|pcarry4
- 2 - H 02 OR2 2 1 0 2 |lpm_add_sub:394|addcore:adder|pcarry5
- 3 - H 02 OR2 2 1 0 1 |lpm_add_sub:394|addcore:adder|pcarry6
- 4 - H 24 AND2 2 0 0 2 |lpm_add_sub:394|addcore:adder|:114
- 2 - H 04 OR2 4 0 0 2 |lpm_add_sub:395|addcore:adder|pcarry1
- 4 - H 15 OR2 2 1 0 2 |lpm_add_sub:395|addcore:adder|pcarry2
- 8 - H 15 OR2 2 1 0 2 |lpm_add_sub:395|addcore:adder|pcarry3
- 1 - H 15 OR2 2 1 0 2 |lpm_add_sub:395|addcore:adder|pcarry4
- 2 - H 15 OR2 2 1 0 2 |lpm_add_sub:395|addcore:adder|pcarry5
- 1 - H 14 OR2 2 1 0 1 |lpm_add_sub:395|addcore:adder|pcarry6
- 6 - H 24 OR2 s 3 0 0 1 |lpm_add_sub:395|addcore:adder|~156~1
- 1 - H 13 OR2 2 1 0 1 |lpm_add_sub:395|addcore:adder|:160
- 2 - H 25 OR2 2 1 0 1 |lpm_add_sub:395|addcore:adder|:161
- 3 - H 06 OR2 2 1 0 1 |lpm_add_sub:395|addcore:adder|:162
- 6 - H 08 AND2 3 0 0 3 |lpm_add_sub:396|addcore:adder|:125
- 4 - H 08 AND2 1 1 0 2 |lpm_add_sub:396|addcore:adder|:129
- 2 - H 08 AND2 3 1 0 2 |lpm_add_sub:396|addcore:adder|:137
- 5 - H 08 OR2 3 0 0 1 |lpm_add_sub:397|addcore:adder|pcarry2
- 1 - H 20 AND2 ! 4 0 0 3 |lpm_add_sub:397|addcore:adder|pcarry3
- 3 - H 20 AND2 ! 2 1 0 3 |lpm_add_sub:397|addcore:adder|pcarry5
- 5 - H 04 OR2 3 0 0 1 |lpm_add_sub:397|addcore:adder|:150
- 6 - H 22 AND2 3 0 0 8 :36
- 8 - H 22 AND2 3 0 0 8 :48
- 5 - H 06 OR2 2 2 0 1 :52
- 4 - H 22 AND2 3 0 0 8 :60
- 1 - H 22 AND2 3 0 0 8 :73
- 3 - H 22 AND2 3 0 0 8 :93
- 2 - H 22 AND2 3 0 0 8 :113
- 7 - H 22 OR2 2 2 0 1 :117
- 2 - H 18 AND2 3 0 0 8 :125
- 7 - H 20 OR2 2 2 0 1 :130
- 3 - H 18 AND2 3 0 0 8 :138
- 5 - H 22 OR2 s 2 2 0 1 ~166~1
- 6 - H 06 OR2 s 2 2 0 1 ~166~2
- 7 - H 06 OR2 s 0 4 0 1 ~166~3
- 8 - H 06 OR2 0 4 0 2 :166
- 3 - H 25 OR2 2 2 0 1 :194
- 3 - H 13 OR2 2 2 0 1 :195
- 1 - H 02 OR2 2 2 0 1 :196
- 5 - H 02 OR2 2 2 0 1 :197
- 6 - H 02 OR2 2 2 0 1 :198
- 3 - H 24 OR2 2 2 0 1 :199
- 3 - H 15 OR2 2 2 0 1 :204
- 5 - H 15 OR2 2 2 0 1 :205
- 4 - H 04 OR2 2 2 0 1 :206
- 7 - H 25 OR2 1 2 0 1 :226
- 4 - H 13 OR2 2 2 0 1 :227
- 6 - H 04 OR2 3 1 0 1 :230
- 4 - H 25 OR2 1 2 0 1 :234
- 5 - H 13 OR2 2 2 0 1 :235
- 5 - H 25 OR2 s 2 2 0 1 ~258~1
- 6 - H 25 OR2 s 2 2 0 1 ~258~2
- 8 - H 25 OR2 s 0 4 0 1 ~258~3
- 1 - H 25 OR2 0 4 0 3 :258
- 6 - H 13 OR2 s 2 2 0 1 ~259~1
- 7 - H 13 OR2 s 2 2 0 1 ~259~2
- 8 - H 13 OR2 s 0 4 0 1 ~259~3
- 2 - H 13 OR2 0 4 0 3 :259
- 4 - H 20 OR2 s 2 2 0 1 ~260~1
- 6 - H 20 OR2 s 1 3 0 1 ~260~2
- 1 - H 08 OR2 s 1 3 0 1 ~260~3
- 2 - H 19 OR2 s 2 2 0 1 ~260~4
- 5 - H 19 OR2 0 4 0 3 :260
- 7 - H 15 OR2 s 2 2 0 1 ~261~1
- 7 - H 08 OR2 s 2 2 0 1 ~261~2
- 8 - H 08 OR2 s 1 3 0 1 ~261~3
- 3 - H 08 OR2 s 1 3 0 1 ~261~4
- 6 - H 15 OR2 0 4 0 3 :261
- 3 - H 04 OR2 s 2 2 0 1 ~262~1
- 7 - H 04 OR2 s 2 2 0 1 ~262~2
- 8 - H 04 OR2 s 0 4 0 1 ~262~3
- 1 - H 04 OR2 0 4 0 3 :262
- 7 - H 24 OR2 s 2 2 0 1 ~263~1
- 2 - H 24 OR2 s 1 3 0 1 ~263~2
- 1 - H 18 OR2 s 2 2 0 1 ~263~3
- 3 - H 50 OR2 s 2 2 0 1 ~263~4
- 4 - H 50 OR2 0 4 0 3 :263
- 8 - H 24 OR2 s 0 2 0 1 ~264~1
- 1 - H 24 OR2 s 2 2 0 1 ~264~2
- 2 - H 20 OR2 s 1 3 0 1 ~264~3
- 8 - H 20 OR2 s 1 2 0 1 ~264~4
- 6 - H 50 OR2 0 4 0 2 :264
- 2 - H 06 OR2 s 2 2 0 1 ~376~1
- 7 - H 19 OR2 s 2 2 0 1 ~377~1
- 6 - H 19 OR2 s 2 2 0 1 ~378~1
- 1 - H 19 OR2 s 2 2 0 1 ~379~1
- 8 - H 50 OR2 s 2 2 0 1 ~380~1
- 7 - H 50 OR2 s 2 2 0 1 ~381~1
- 4 - H 06 DFFE + 2 2 1 0 :383
- 1 - H 06 DFFE + 2 2 1 0 :384
- 8 - H 19 DFFE + 2 2 1 0 :385
- 4 - H 19 DFFE + 2 2 1 0 :386
- 3 - H 19 DFFE + 2 2 1 0 :387
- 1 - H 50 DFFE + 2 2 1 0 :388
- 5 - H 50 DFFE + 2 2 1 0 :389
- 2 - H 50 DFFE + 2 2 1 0 :390
- 5 - H 20 AND2 ! 2 1 1 0 :392
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: c:\maxplus2\verilog7\alu.rpt
alu
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 26/208( 12%) 34/104( 32%) 1/104( 0%) 7/16( 43%) 5/16( 31%) 0/16( 0%)
I: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
J: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
K: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
L: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
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