📄 for4bitmux2.rpt
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Device-Specific Information: c:\maxplus2\verilog7\for4bitmux2.rpt
for4bitmux2
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
b0 : INPUT;
b1 : INPUT;
b2 : INPUT;
b3 : INPUT;
sel : INPUT;
-- Node name is 'ds0~1'
-- Equation name is 'ds0~1', location is LC2_C32, type is buried.
-- synthesized logic cell
_LC2_C32 = LCELL( sel);
-- Node name is 'ds0'
-- Equation name is 'ds0', type is output
ds0 = !_LC2_C32;
-- Node name is 'ds1~1'
-- Equation name is 'ds1~1', location is LC8_C32, type is buried.
-- synthesized logic cell
_LC8_C32 = LCELL( sel);
-- Node name is 'ds1'
-- Equation name is 'ds1', type is output
ds1 = _LC8_C32;
-- Node name is 'ds2'
-- Equation name is 'ds2', type is output
ds2 = GND;
-- Node name is 'ds3'
-- Equation name is 'ds3', type is output
ds3 = GND;
-- Node name is 'y0'
-- Equation name is 'y0', type is output
y0 = _LC1_C32;
-- Node name is 'y1'
-- Equation name is 'y1', type is output
y1 = _LC6_C32;
-- Node name is 'y2'
-- Equation name is 'y2', type is output
y2 = _LC5_C32;
-- Node name is 'y3'
-- Equation name is 'y3', type is output
y3 = _LC7_C32;
-- Node name is ':28'
-- Equation name is '_LC7_C32', type is buried
_LC7_C32 = LCELL( _EQ001);
_EQ001 = b3 & !sel
# a3 & sel;
-- Node name is ':29'
-- Equation name is '_LC5_C32', type is buried
_LC5_C32 = LCELL( _EQ002);
_EQ002 = b2 & !sel
# a2 & sel;
-- Node name is ':30'
-- Equation name is '_LC6_C32', type is buried
_LC6_C32 = LCELL( _EQ003);
_EQ003 = b1 & !sel
# a1 & sel;
-- Node name is ':31'
-- Equation name is '_LC1_C32', type is buried
_LC1_C32 = LCELL( _EQ004);
_EQ004 = b0 & !sel
# a0 & sel;
Project Information c:\maxplus2\verilog7\for4bitmux2.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:05
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:07
Memory Allocated
-----------------
Peak memory allocated during compilation = 49,928K
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