cyclecounter.rpt

多工器ｖｅｒｉｌｏｇ設計1對多快速解碼提供控制功能

-- Node name is '|btoseven:8|:260' 
-- Equation name is '_LC2_L15', type is buried 
_LC2_L15 = LCELL( _EQ017);
  _EQ017 =  _LC3_L15
         #  _LC5_L15
         #  _LC5_L14
         #  _LC7_L15;

-- Node name is '|btoseven:8|~263~1' 
-- Equation name is '_LC5_L14', type is buried 
-- synthesized logic cell 
_LC5_L14 = LCELL( _EQ018);
  _EQ018 =  _LC3_L14
         #  _LC1_L15;

-- Node name is '|btoseven:8|~263~2' 
-- Equation name is '_LC7_L14', type is buried 
-- synthesized logic cell 
_LC7_L14 = LCELL( _EQ019);
  _EQ019 = !_LC1_D25 & !_LC4_D24 &  _LC4_D25 & !_LC8_D25
         #  _LC1_D25 & !_LC4_D24 &  _LC4_D25 &  _LC8_D25;

-- Node name is '|btoseven:8|:263' 
-- Equation name is '_LC4_L14', type is buried 
_LC4_L14 = LCELL( _EQ020);
  _EQ020 =  _LC5_L14
         #  _LC7_L14
         #  _LC6_L14
         #  _LC8_L14;

-- Node name is '|btoseven:8|~266~1' 
-- Equation name is '_LC1_L14', type is buried 
-- synthesized logic cell 
_LC1_L14 = LCELL( _EQ021);
  _EQ021 = !_LC1_D25 &  _LC4_D24 &  _LC4_D25 & !_LC8_D25
         #  _LC1_D25 & !_LC4_D24 &  _LC4_D25 & !_LC8_D25;

-- Node name is '|btoseven:8|~266~2' 
-- Equation name is '_LC5_L13', type is buried 
-- synthesized logic cell 
_LC5_L13 = LCELL( _EQ022);
  _EQ022 = !_LC4_D24 &  _LC4_D25 &  _LC8_D25;

-- Node name is '|btoseven:8|:266' 
-- Equation name is '_LC2_L18', type is buried 
_LC2_L18 = LCELL( _EQ023);
  _EQ023 =  _LC2_L14
         #  _LC2_L13
         #  _LC1_L14
         #  _LC5_L13;

-- Node name is '|cnt8:1|lpm_add_sub:28|addcore:adder|:121' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_D25', type is buried 
_LC7_D25 = LCELL( _EQ024);
  _EQ024 =  _LC3_D25 &  _LC6_D25;

-- Node name is '|cnt8:1|lpm_add_sub:28|addcore:adder|:129' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_D24', type is buried 
_LC5_D24 = LCELL( _EQ025);
  _EQ025 =  _LC2_D25 &  _LC3_D25 &  _LC5_D25 &  _LC6_D25;

-- Node name is '|cnt8:1|lpm_add_sub:28|addcore:adder|:133' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_D24', type is buried 
_LC8_D24 = LCELL( _EQ026);
  _EQ026 =  _LC3_D24 &  _LC5_D24;

-- Node name is '|cnt8:1|lpm_add_sub:28|addcore:adder|:137' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_D24', type is buried 
_LC6_D24 = LCELL( _EQ027);
  _EQ027 =  _LC1_D24 &  _LC3_D24 &  _LC5_D24;

-- Node name is '|cnt8:1|:12' 
-- Equation name is '_LC7_D24', type is buried 
_LC7_D24 = DFFE( _EQ028, GLOBAL( clk),  VCC,  VCC,  en);
  _EQ028 = !_LC2_D24 &  _LC7_D24
         # !_LC6_D24 &  _LC7_D24
         #  _LC2_D24 &  _LC6_D24 & !_LC7_D24;

-- Node name is '|cnt8:1|:13' 
-- Equation name is '_LC2_D24', type is buried 
_LC2_D24 = DFFE( _EQ029, GLOBAL( clk),  VCC,  VCC,  en);
  _EQ029 = !_LC1_D24 &  _LC2_D24
         #  _LC2_D24 & !_LC8_D24
         #  _LC1_D24 & !_LC2_D24 &  _LC8_D24;

-- Node name is '|cnt8:1|:14' 
-- Equation name is '_LC1_D24', type is buried 
_LC1_D24 = DFFE( _EQ030, GLOBAL( clk),  VCC,  VCC,  en);
  _EQ030 =  _LC1_D24 & !_LC3_D24
         #  _LC1_D24 & !_LC5_D24
         # !_LC1_D24 &  _LC3_D24 &  _LC5_D24;

-- Node name is '|cnt8:1|:15' 
-- Equation name is '_LC3_D24', type is buried 
_LC3_D24 = DFFE( _EQ031, GLOBAL( clk),  VCC,  VCC,  en);
  _EQ031 =  _LC3_D24 & !_LC5_D24
         # !_LC3_D24 &  _LC5_D24;

-- Node name is '|cnt8:1|:16' 
-- Equation name is '_LC2_D25', type is buried 
_LC2_D25 = DFFE( _EQ032, GLOBAL( clk),  VCC,  VCC,  en);
  _EQ032 =  _LC2_D25 & !_LC5_D25
         #  _LC2_D25 & !_LC7_D25
         # !_LC2_D25 &  _LC5_D25 &  _LC7_D25;

-- Node name is '|cnt8:1|:17' 
-- Equation name is '_LC5_D25', type is buried 
_LC5_D25 = DFFE( _EQ033, GLOBAL( clk),  VCC,  VCC,  en);
  _EQ033 =  _LC5_D25 & !_LC6_D25
         # !_LC3_D25 &  _LC5_D25
         #  _LC3_D25 & !_LC5_D25 &  _LC6_D25;

-- Node name is '|cnt8:1|:18' 
-- Equation name is '_LC6_D25', type is buried 
_LC6_D25 = DFFE( _EQ034, GLOBAL( clk),  VCC,  VCC,  en);
  _EQ034 = !_LC3_D25 &  _LC6_D25
         #  _LC3_D25 & !_LC6_D25;

-- Node name is '|cnt8:1|:19' 
-- Equation name is '_LC3_D25', type is buried 
_LC3_D25 = DFFE(!_LC3_D25, GLOBAL( clk),  VCC,  VCC,  en);

-- Node name is '|fourbitmux2:2|:28' 
-- Equation name is '_LC4_D24', type is buried 
!_LC4_D24 = _LC4_D24~NOT;
_LC4_D24~NOT = LCELL( _EQ035);
  _EQ035 = !clk & !_LC2_D25
         #  clk & !_LC7_D24
         # !_LC2_D25 & !_LC7_D24;

-- Node name is '|fourbitmux2:2|:29' 
-- Equation name is '_LC8_D25', type is buried 
_LC8_D25 = LCELL( _EQ036);
  _EQ036 = !clk &  _LC5_D25
         #  clk &  _LC2_D24;

-- Node name is '|fourbitmux2:2|:30' 
-- Equation name is '_LC1_D25', type is buried 
_LC1_D25 = LCELL( _EQ037);
  _EQ037 = !clk &  _LC6_D25
         #  clk &  _LC1_D24;

-- Node name is '|fourbitmux2:2|:31' 
-- Equation name is '_LC4_D25', type is buried 
_LC4_D25 = LCELL( _EQ038);
  _EQ038 = !clk &  _LC3_D25
         #  clk &  _LC3_D24;



Project Information                      c:\maxplus2\verilog5\cyclecounter.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 55,837K