cyclecounter.rpt

多工器ｖｅｒｉｌｏｇ設計1對多快速解碼提供控制功能

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Device-Specific Information:             c:\maxplus2\verilog5\cyclecounter.rpt
cyclecounter

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       14         clk


Device-Specific Information:             c:\maxplus2\verilog5\cyclecounter.rpt
cyclecounter

** EQUATIONS **

clk      : INPUT;
en       : INPUT;

-- Node name is 'ds0~1' 
-- Equation name is 'ds0~1', location is LC1_E20, type is buried.
-- synthesized logic cell 
_LC1_E20 = LCELL( clk);

-- Node name is 'ds0' 
-- Equation name is 'ds0', type is output 
ds0      = !_LC1_E20;

-- Node name is 'ds1~1' 
-- Equation name is 'ds1~1', location is LC1_C20, type is buried.
-- synthesized logic cell 
_LC1_C20 = LCELL( clk);

-- Node name is 'ds1' 
-- Equation name is 'ds1', type is output 
ds1      =  _LC1_C20;

-- Node name is 'ds2' 
-- Equation name is 'ds2', type is output 
ds2      =  GND;

-- Node name is 'ds3' 
-- Equation name is 'ds3', type is output 
ds3      =  GND;

-- Node name is 'sout0' 
-- Equation name is 'sout0', type is output 
sout0    =  _LC2_L18;

-- Node name is 'sout1' 
-- Equation name is 'sout1', type is output 
sout1    =  _LC4_L14;

-- Node name is 'sout2' 
-- Equation name is 'sout2', type is output 
sout2    =  _LC2_L15;

-- Node name is 'sout3' 
-- Equation name is 'sout3', type is output 
sout3    =  _LC6_L15;

-- Node name is 'sout4' 
-- Equation name is 'sout4', type is output 
sout4    =  _LC8_L13;

-- Node name is 'sout5' 
-- Equation name is 'sout5', type is output 
sout5    =  _LC1_L18;

-- Node name is 'sout6' 
-- Equation name is 'sout6', type is output 
sout6    =  _LC4_L10;

-- Node name is 'sout7' 
-- Equation name is 'sout7', type is output 
sout7    =  GND;

-- Node name is '|btoseven:8|:39' 
-- Equation name is '_LC6_L14', type is buried 
_LC6_L14 = LCELL( _EQ001);
  _EQ001 =  _LC1_D25 & !_LC4_D24 & !_LC4_D25 & !_LC8_D25;

-- Node name is '|btoseven:8|:65' 
-- Equation name is '_LC3_L14', type is buried 
_LC3_L14 = LCELL( _EQ002);
  _EQ002 = !_LC1_D25 & !_LC4_D24 & !_LC4_D25 &  _LC8_D25;

-- Node name is '|btoseven:8|:91' 
-- Equation name is '_LC5_L15', type is buried 
_LC5_L15 = LCELL( _EQ003);
  _EQ003 =  _LC1_D25 & !_LC4_D24 & !_LC4_D25 &  _LC8_D25;

-- Node name is '|btoseven:8|:130' 
-- Equation name is '_LC4_L13', type is buried 
_LC4_L13 = LCELL( _EQ004);
  _EQ004 = !_LC1_D25 &  _LC4_D24 &  _LC4_D25 & !_LC8_D25;

-- Node name is '|btoseven:8|:248' 
-- Equation name is '_LC4_L10', type is buried 
_LC4_L10 = LCELL( _EQ005);
  _EQ005 =  _LC1_D25 &  _LC4_D24
         # !_LC1_D25 &  _LC4_D25 &  _LC8_D25
         #  _LC4_D24 &  _LC4_D25
         #  _LC1_D25 & !_LC4_D25
         #  _LC4_D24 & !_LC8_D25
         #  _LC1_D25 & !_LC8_D25
         # !_LC4_D24 & !_LC4_D25 &  _LC8_D25;

-- Node name is '|btoseven:8|~251~1' 
-- Equation name is '_LC2_L14', type is buried 
-- synthesized logic cell 
_LC2_L14 = LCELL( _EQ006);
  _EQ006 =  _LC1_D25 & !_LC4_D25 &  _LC8_D25
         #  _LC1_D25 &  _LC4_D24 &  _LC8_D25
         # !_LC1_D25 & !_LC4_D25 & !_LC8_D25
         #  _LC4_D24 & !_LC4_D25 &  _LC8_D25;

-- Node name is '|btoseven:8|~251~2' 
-- Equation name is '_LC3_L15', type is buried 
-- synthesized logic cell 
_LC3_L15 = LCELL( _EQ007);
  _EQ007 =  _LC1_D25 &  _LC4_D24 &  _LC4_D25 & !_LC8_D25
         # !_LC1_D25 & !_LC4_D24 &  _LC4_D25 &  _LC8_D25;

-- Node name is '|btoseven:8|~251~3' 
-- Equation name is '_LC8_L15', type is buried 
-- synthesized logic cell 
_LC8_L15 = LCELL( _EQ008);
  _EQ008 =  _LC1_D25 & !_LC4_D25 &  _LC8_D25
         # !_LC1_D25 & !_LC4_D25 & !_LC8_D25
         #  _LC4_D24 & !_LC4_D25 &  _LC8_D25;

-- Node name is '|btoseven:8|:251' 
-- Equation name is '_LC1_L18', type is buried 
_LC1_L18 = LCELL( _EQ009);
  _EQ009 =  _LC4_L13
         #  _LC3_L15
         #  _LC3_L14
         #  _LC2_L14;

-- Node name is '|btoseven:8|~254~1' 
-- Equation name is '_LC2_L13', type is buried 
-- synthesized logic cell 
_LC2_L13 = LCELL( _EQ010);
  _EQ010 =  _LC1_D25 & !_LC4_D25 & !_LC8_D25;

-- Node name is '|btoseven:8|~254~2' 
-- Equation name is '_LC8_L14', type is buried 
-- synthesized logic cell 
_LC8_L14 = LCELL( _EQ011);
  _EQ011 =  _LC1_D25 &  _LC4_D24 & !_LC4_D25 &  _LC8_D25
         # !_LC1_D25 & !_LC4_D25 & !_LC8_D25;

-- Node name is '|btoseven:8|~254~3' 
-- Equation name is '_LC4_L15', type is buried 
-- synthesized logic cell 
_LC4_L15 = LCELL( _EQ012);
  _EQ012 =  _LC1_D25 &  _LC4_D24 &  _LC4_D25 & !_LC8_D25
         # !_LC1_D25 &  _LC4_D24 &  _LC4_D25 &  _LC8_D25;

-- Node name is '|btoseven:8|:254' 
-- Equation name is '_LC8_L13', type is buried 
_LC8_L13 = LCELL( _EQ013);
  _EQ013 =  _LC4_L15
         #  _LC2_L14
         #  _LC2_L13;

-- Node name is '|btoseven:8|~257~1' 
-- Equation name is '_LC1_L15', type is buried 
-- synthesized logic cell 
_LC1_L15 = LCELL( _EQ014);
  _EQ014 =  _LC1_D25 &  _LC4_D24 & !_LC4_D25 & !_LC8_D25
         # !_LC1_D25 &  _LC4_D24 &  _LC4_D25
         #  _LC1_D25 & !_LC4_D24 &  _LC4_D25 & !_LC8_D25;

-- Node name is '|btoseven:8|:257' 
-- Equation name is '_LC6_L15', type is buried 
_LC6_L15 = LCELL( _EQ015);
  _EQ015 =  _LC8_L15
         #  _LC6_L14
         #  _LC3_L15
         #  _LC1_L15;

-- Node name is '|btoseven:8|~260~1' 
-- Equation name is '_LC7_L15', type is buried 
-- synthesized logic cell 
_LC7_L15 = LCELL( _EQ016);
  _EQ016 = !_LC1_D25 & !_LC4_D25 & !_LC8_D25
         # !_LC1_D25 & !_LC4_D24 & !_LC8_D25
         #  _LC1_D25 & !_LC4_D24 &  _LC4_D25 &  _LC8_D25;