btoseven.rpt

多工器ｖｅｒｉｌｏｇ設計1對多快速解碼提供控制功能

  _EQ001 = !bin0 & !bin1 & !bin2 & !bin3;

-- Node name is ':39' 
-- Equation name is '_LC2_A38', type is buried 
_LC2_A38 = LCELL( _EQ002);
  _EQ002 = !bin0 &  bin1 & !bin2 & !bin3;

-- Node name is ':91' 
-- Equation name is '_LC4_A2', type is buried 
_LC4_A2  = LCELL( _EQ003);
  _EQ003 = !bin0 &  bin1 &  bin2 & !bin3;

-- Node name is ':104' 
-- Equation name is '_LC5_A38', type is buried 
_LC5_A38 = LCELL( _EQ004);
  _EQ004 =  bin0 &  bin1 &  bin2 & !bin3;

-- Node name is ':117' 
-- Equation name is '_LC1_A14', type is buried 
_LC1_A14 = LCELL( _EQ005);
  _EQ005 = !bin0 & !bin1 & !bin2 &  bin3;

-- Node name is '~169~1' 
-- Equation name is '~169~1', location is LC5_A14, type is buried.
-- synthesized logic cell 
_LC5_A14 = LCELL( _EQ006);
  _EQ006 =  bin2 &  bin3;

-- Node name is ':195' 
-- Equation name is '_LC7_A14', type is buried 
_LC7_A14 = LCELL( _EQ007);
  _EQ007 = !bin0 &  bin1 &  bin2 &  bin3;

-- Node name is '~248~1' 
-- Equation name is '~248~1', location is LC6_A14, type is buried.
-- synthesized logic cell 
_LC6_A14 = LCELL( _EQ008);
  _EQ008 =  bin0 &  bin1 &  _LC5_A14
         #  _LC1_A2;

-- Node name is ':248' 
-- Equation name is '_LC2_A14', type is buried 
_LC2_A14 = LCELL( _EQ009);
  _EQ009 =  _LC6_A14
         #  _LC7_A14
         #  _LC1_A14
         #  _LC2_A38;

-- Node name is '~251~1' 
-- Equation name is '~251~1', location is LC2_A2, type is buried.
-- synthesized logic cell 
_LC2_A2  = LCELL( _EQ010);
  _EQ010 =  bin0 &  bin1 & !bin2 &  bin3
         #  bin0 & !bin1 &  bin2 & !bin3;

-- Node name is '~251~2' 
-- Equation name is '~251~2', location is LC7_A2, type is buried.
-- synthesized logic cell 
_LC7_A2  = LCELL( _EQ011);
  _EQ011 =  bin1 &  bin2 &  bin3
         # !bin1 & !bin2 &  bin3
         # !bin0 & !bin1 & !bin3
         # !bin0 &  bin2 & !bin3
         # !bin0 & !bin1 &  bin2;

-- Node name is ':251' 
-- Equation name is '_LC8_A2', type is buried 
_LC8_A2  = LCELL( _EQ012);
  _EQ012 =  _LC7_A2
         #  _LC2_A2;

-- Node name is '~254~1' 
-- Equation name is '~254~1', location is LC6_A38, type is buried.
-- synthesized logic cell 
_LC6_A38 = LCELL( _EQ013);
  _EQ013 =  bin1 &  bin2 &  bin3
         # !bin0 & !bin1 & !bin2
         # !bin0 &  bin1 &  bin2
         # !bin0 &  bin3;

-- Node name is ':254' 
-- Equation name is '_LC1_A38', type is buried 
_LC1_A38 = LCELL( _EQ014);
  _EQ014 =  bin1 &  bin3
         # !bin0 & !bin2
         # !bin0 &  bin1
         #  bin2 &  bin3;

-- Node name is '~257~1' 
-- Equation name is '~257~1', location is LC5_A2, type is buried.
-- synthesized logic cell 
_LC5_A2  = LCELL( _EQ015);
  _EQ015 =  bin0 &  bin1 & !bin2 & !bin3
         # !bin0 &  bin3
         # !bin0 & !bin1 & !bin2
         # !bin0 &  bin1 &  bin2
         # !bin1 &  bin3;

-- Node name is ':257' 
-- Equation name is '_LC6_A2', type is buried 
_LC6_A2  = LCELL( _EQ016);
  _EQ016 =  _LC5_A2
         #  _LC2_A2
         #  _LC2_A38;

-- Node name is '~260~1' 
-- Equation name is '~260~1', location is LC1_A2, type is buried.
-- synthesized logic cell 
_LC1_A2  = LCELL( _EQ017);
  _EQ017 =  _LC2_A2
         #  _LC3_A2
         #  _LC4_A2;

-- Node name is ':260' 
-- Equation name is '_LC8_A14', type is buried 
_LC8_A14 = LCELL( _EQ018);
  _EQ018 =  _LC1_A2
         #  _LC1_A14
         #  _LC3_A14
         #  _LC4_A14;

-- Node name is '~263~1' 
-- Equation name is '~263~1', location is LC3_A2, type is buried.
-- synthesized logic cell 
_LC3_A2  = LCELL( _EQ019);
  _EQ019 = !bin0 & !bin1 &  bin2 & !bin3
         #  bin0 & !bin1 &  bin3
         #  bin0 &  bin1 & !bin2 & !bin3
         # !bin0 &  bin1 & !bin2 &  bin3;

-- Node name is '~263~2' 
-- Equation name is '~263~2', location is LC4_A14, type is buried.
-- synthesized logic cell 
_LC4_A14 = LCELL( _EQ020);
  _EQ020 =  bin0 & !bin1 & !bin2 & !bin3
         #  bin0 &  bin1 &  bin2 & !bin3;

-- Node name is ':263' 
-- Equation name is '_LC4_A38', type is buried 
_LC4_A38 = LCELL( _EQ021);
  _EQ021 =  bin0 &  bin1 & !bin3
         # !bin0 & !bin1 & !bin3
         #  bin0 & !bin1 &  bin3
         # !bin0 & !bin2
         # !bin0 &  bin1 &  bin3
         # !bin1 & !bin2
         # !bin2 & !bin3;

-- Node name is '~266~1' 
-- Equation name is '~266~1', location is LC7_A38, type is buried.
-- synthesized logic cell 
_LC7_A38 = LCELL( _EQ022);
  _EQ022 =  bin0 & !bin1 &  bin2 & !bin3
         #  bin0 & !bin1 & !bin2 &  bin3
         #  bin0 &  bin1 & !bin2 & !bin3;

-- Node name is ':266' 
-- Equation name is '_LC3_A38', type is buried 
_LC3_A38 = LCELL( _EQ023);
  _EQ023 =  _LC5_A38
         #  _LC2_A38
         #  _LC6_A38
         #  _LC7_A38;



Project Information                          c:\maxplus2\verilog5\btoseven.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 51,698K