📄 btoseven.rpt
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Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 10/4992 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 EA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Total(LC/EC)
A: 0 8 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
G: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
H: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
I: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
J: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
K: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
L: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 8 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23/0
Device-Specific Information: c:\maxplus2\verilog5\btoseven.rpt
btoseven
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
R12 - - - -- INPUT ^ 0 0 0 16 bin0
V11 - - - -- INPUT ^ 0 0 0 16 bin1
E12 - - - -- INPUT ^ 0 0 0 16 bin2
H11 - - - -- INPUT ^ 0 0 0 16 bin3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\maxplus2\verilog5\btoseven.rpt
btoseven
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
Y15 - - - 38 OUTPUT 0 1 0 0 sout0
E20 - - A -- OUTPUT 0 1 0 0 sout1
F1 - - A -- OUTPUT 0 1 0 0 sout2
E2 - - A -- OUTPUT 0 1 0 0 sout3
D21 - - A -- OUTPUT 0 1 0 0 sout4
D1 - - A -- OUTPUT 0 1 0 0 sout5
C1 - - A -- OUTPUT 0 1 0 0 sout6
AA21 - - - 51 OUTPUT 0 0 0 0 sout7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\maxplus2\verilog5\btoseven.rpt
btoseven
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - A 14 AND2 4 0 0 1 :13
- 2 - A 38 AND2 4 0 0 3 :39
- 4 - A 02 AND2 4 0 0 1 :91
- 5 - A 38 AND2 4 0 0 1 :104
- 1 - A 14 AND2 4 0 0 2 :117
- 5 - A 14 AND2 s 2 0 0 1 ~169~1
- 7 - A 14 AND2 4 0 0 1 :195
- 6 - A 14 OR2 s 2 2 0 1 ~248~1
- 2 - A 14 OR2 0 4 1 0 :248
- 2 - A 02 OR2 s 4 0 0 3 ~251~1
- 7 - A 02 OR2 s 4 0 0 1 ~251~2
- 8 - A 02 OR2 0 2 1 0 :251
- 6 - A 38 OR2 s 4 0 0 1 ~254~1
- 1 - A 38 OR2 4 0 1 0 :254
- 5 - A 02 OR2 s 4 0 0 1 ~257~1
- 6 - A 02 OR2 0 3 1 0 :257
- 1 - A 02 OR2 s 0 3 0 2 ~260~1
- 8 - A 14 OR2 0 4 1 0 :260
- 3 - A 02 OR2 s 4 0 0 1 ~263~1
- 4 - A 14 OR2 s 4 0 0 1 ~263~2
- 4 - A 38 OR2 4 0 1 0 :263
- 7 - A 38 OR2 s 4 0 0 1 ~266~1
- 3 - A 38 OR2 0 4 1 0 :266
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: c:\maxplus2\verilog5\btoseven.rpt
btoseven
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/208( 1%) 3/104( 2%) 1/104( 0%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
B: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
I: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
J: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
K: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
L: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
37: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
38: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
39: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
40: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
41: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
42: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
43: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
44: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
45: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
46: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
47: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
48: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
49: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
50: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
51: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
52: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\maxplus2\verilog5\btoseven.rpt
btoseven
** EQUATIONS **
bin0 : INPUT;
bin1 : INPUT;
bin2 : INPUT;
bin3 : INPUT;
-- Node name is 'sout0'
-- Equation name is 'sout0', type is output
sout0 = _LC3_A38;
-- Node name is 'sout1'
-- Equation name is 'sout1', type is output
sout1 = _LC4_A38;
-- Node name is 'sout2'
-- Equation name is 'sout2', type is output
sout2 = _LC8_A14;
-- Node name is 'sout3'
-- Equation name is 'sout3', type is output
sout3 = _LC6_A2;
-- Node name is 'sout4'
-- Equation name is 'sout4', type is output
sout4 = _LC1_A38;
-- Node name is 'sout5'
-- Equation name is 'sout5', type is output
sout5 = _LC8_A2;
-- Node name is 'sout6'
-- Equation name is 'sout6', type is output
sout6 = _LC2_A14;
-- Node name is 'sout7'
-- Equation name is 'sout7', type is output
sout7 = GND;
-- Node name is ':13'
-- Equation name is '_LC3_A14', type is buried
_LC3_A14 = LCELL( _EQ001);
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