📄 cnt8.rpt
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Device-Specific Information: c:\maxplus2\verilog5\cnt8.rpt
cnt8
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 mclk
Device-Specific Information: c:\maxplus2\verilog5\cnt8.rpt
cnt8
** EQUATIONS **
en : INPUT;
mclk : INPUT;
-- Node name is 'cq0'
-- Equation name is 'cq0', type is output
cq0 = _LC5_K32;
-- Node name is 'cq1'
-- Equation name is 'cq1', type is output
cq1 = _LC8_K32;
-- Node name is 'cq2'
-- Equation name is 'cq2', type is output
cq2 = _LC2_K32;
-- Node name is 'cq3'
-- Equation name is 'cq3', type is output
cq3 = _LC2_K36;
-- Node name is 'cq4'
-- Equation name is 'cq4', type is output
cq4 = _LC5_K36;
-- Node name is 'cq5'
-- Equation name is 'cq5', type is output
cq5 = _LC7_K36;
-- Node name is 'cq6'
-- Equation name is 'cq6', type is output
cq6 = _LC6_K36;
-- Node name is 'cq7'
-- Equation name is 'cq7', type is output
cq7 = _LC3_K36;
-- Node name is '|lpm_add_sub:28|addcore:adder|:125' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_K36', type is buried
_LC1_K36 = LCELL( _EQ001);
_EQ001 = _LC2_K32 & _LC5_K32 & _LC8_K32;
-- Node name is '|lpm_add_sub:28|addcore:adder|:129' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_K36', type is buried
_LC4_K36 = LCELL( _EQ002);
_EQ002 = _LC1_K36 & _LC2_K36;
-- Node name is '|lpm_add_sub:28|addcore:adder|:137' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_K36', type is buried
_LC8_K36 = LCELL( _EQ003);
_EQ003 = _LC1_K36 & _LC2_K36 & _LC5_K36 & _LC7_K36;
-- Node name is ':12'
-- Equation name is '_LC3_K36', type is buried
_LC3_K36 = DFFE( _EQ004, GLOBAL( mclk), VCC, VCC, en);
_EQ004 = _LC3_K36 & !_LC6_K36
# _LC3_K36 & !_LC8_K36
# !_LC3_K36 & _LC6_K36 & _LC8_K36;
-- Node name is ':13'
-- Equation name is '_LC6_K36', type is buried
_LC6_K36 = DFFE( _EQ005, GLOBAL( mclk), VCC, VCC, en);
_EQ005 = _LC6_K36 & !_LC8_K36
# !_LC6_K36 & _LC8_K36;
-- Node name is ':14'
-- Equation name is '_LC7_K36', type is buried
_LC7_K36 = DFFE( _EQ006, GLOBAL( mclk), VCC, VCC, en);
_EQ006 = !_LC4_K36 & _LC7_K36
# !_LC5_K36 & _LC7_K36
# _LC4_K36 & _LC5_K36 & !_LC7_K36;
-- Node name is ':15'
-- Equation name is '_LC5_K36', type is buried
_LC5_K36 = DFFE( _EQ007, GLOBAL( mclk), VCC, VCC, en);
_EQ007 = !_LC2_K36 & _LC5_K36
# !_LC1_K36 & _LC5_K36
# _LC1_K36 & _LC2_K36 & !_LC5_K36;
-- Node name is ':16'
-- Equation name is '_LC2_K36', type is buried
_LC2_K36 = DFFE( _EQ008, GLOBAL( mclk), VCC, VCC, en);
_EQ008 = !_LC1_K36 & _LC2_K36
# _LC1_K36 & !_LC2_K36;
-- Node name is ':17'
-- Equation name is '_LC2_K32', type is buried
_LC2_K32 = DFFE( _EQ009, GLOBAL( mclk), VCC, VCC, en);
_EQ009 = _LC2_K32 & !_LC8_K32
# _LC2_K32 & !_LC5_K32
# !_LC2_K32 & _LC5_K32 & _LC8_K32;
-- Node name is ':18'
-- Equation name is '_LC8_K32', type is buried
_LC8_K32 = DFFE( _EQ010, GLOBAL( mclk), VCC, VCC, en);
_EQ010 = !_LC5_K32 & _LC8_K32
# _LC5_K32 & !_LC8_K32;
-- Node name is ':19'
-- Equation name is '_LC5_K32', type is buried
_LC5_K32 = DFFE(!_LC5_K32, GLOBAL( mclk), VCC, VCC, en);
Project Information c:\maxplus2\verilog5\cnt8.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 49,383K
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