set_pll.vhd

VHDL编写的ADI锁相环控制程序

---------ADF4110-------
library ieee;
use  ieee.std_logic_1164.all;
USE  IEEE.STD_LOGIC_UNSIGNED.ALL;
use  IEEE.std_logic_arith.all;
entity set_pll is
   port( reset, clk: in std_logic;
         D_out,D_clk,LE: out std_logic;
         CE: out   std_logic );
end set_pll;
architecture PCI of set_pll is
signal R_REG,N_REG,INI_REG,FUN_REG : std_logic_vector(23 downto 0);-----R，N，INT，Function四个寄存器-------
signal count : std_logic_vector( 4  downto 0);--------每个寄存器的24个比特-----------
signal count_reg: std_logic_vector(2  downto 0);------ 4个寄存器指定与选择------
signal DD_clk: std_logic;
begin
 
 D_clk<=not(DD_clk);
CE<='1';
----------------------------------------------------------------
time_count: process(reset,clk,count)--------
            begin
            if reset='1' then
                count<="00000";
            else
                if clk'event and clk='1' then
                     if count<"11001" then
                        count<=count +1;
                      else
                        count<="00000";
                      end if;
                end if;
             end if;
           end process time_count;

every_reg: process(reset,count_reg,clk,count)
           begin
           if reset='1' then
            count_reg<="000";
           else
                if clk'event and clk='1' then
                    if count="11001" then
                         if count_reg< "111" then 
                          count_reg<=count_reg+1;
                          end if;
                    end if;
                end if;
           end if;
          end process every_reg;

---------------------------------------------------------------------
LE_GENER: process(clk,count,reset)
          begin
          if reset='1' then
            LE<='0';
          else
              if clk'event and clk='1' then

                  if count="11001" and count_reg< "011" then
                    LE<='1' ;
                 else
                    LE<='0';
                    
                 end if;
             end if;
         end if;
      end process LE_GENER;

D_CLK_GEN: process(clk,reset,count_reg,count,DD_clk)
           begin
             if reset='1' then
                DD_clk<='1';
             else
                if count_reg<"011"  then
                    if  count<"11001" then
                        DD_clk<=clk;
                    else
                     DD_clk<='1';
                    end if;
               end if;
           end if;
          end process D_CLK_GEN;


        
-------------------------------------------------------------------

send_data: process(reset,R_REG,N_REG,INI_REG,FUN_REG,count,DD_clk)
   begin
    if reset='1' then
      R_REG<=  "010000000000011001000000";
      N_REG<=  "000000000001011100000001";
      INI_REG<="110011011011110010100011"; 

    --  FUN_REG<="010011011000000001110010";
       

  
    else
       
       if DD_clk'event and DD_clk='1' then
       case count_reg is
                when "000"  =>         if count<"11001" then
                                             D_out<=INI_REG(23);                    
                                             INI_loop:   for k in 23 downto 1 loop
                                                        INI_REG(k)<=INI_REG(k-1);
                                                         end loop INI_loop;                                            

                                       end if;
                when "001"  =>  
                                       if count<"11001" then
                                             D_out<=R_REG(23);                    
                                             R_loop:   for k in 23 downto 1 loop
                                                        R_REG(k)<=R_REG(k-1);
                                                         end loop R_loop;
                                            
                                       end if;
                                   
                when "010"  => 
                                       if count<"11001" then
                                             D_out<=N_REG(23);                    
                                             N_loop:   for k in 23 downto 1 loop
                                                        N_REG(k)<=N_REG(k-1);
                                                         end loop N_loop;
                                                                                   
                                       end if;  
                                  
  --              when "111"  =>  
    --                                   if count<"11001" then
   --                                          D_out<=FUN_REG(23);                    
    --                                         FUN_loop:   for k in 23 downto 1 loop
   --                                                     FUN_REG(k)<=FUN_REG(k-1);
   ----                                                      end loop FUN_loop;
                                            
        --                               end if;
                                   
             when others=> null;
          end case;
     end if;
    end if;
   end process send_data;
end architecture PCI;