de2_usb_api.tan.qmsg

Altera de2开发板提供的配套软件程序

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "13 " "Warning: Found 13 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "AUDIO_DAC:u11\|oAUD_BCK " "Info: Detected ripple clock \"AUDIO_DAC:u11\|oAUD_BCK\" as buffer" {  } { { "AUDIO_DAC.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/AUDIO_DAC.v" 48 -1 0 } } { "i:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "i:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "AUDIO_DAC:u11\|oAUD_BCK" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "AUDIO_DAC:u11\|LRCK_2X " "Info: Detected ripple clock \"AUDIO_DAC:u11\|LRCK_2X\" as buffer" {  } { { "AUDIO_DAC.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/AUDIO_DAC.v" 73 -1 0 } } { "i:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "i:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "AUDIO_DAC:u11\|LRCK_2X" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "AUDIO_DAC:u11\|LRCK_1X " "Info: Detected ripple clock \"AUDIO_DAC:u11\|LRCK_1X\" as buffer" {  } { { "AUDIO_DAC.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/AUDIO_DAC.v" 99 -1 0 } } { "i:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "i:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "AUDIO_DAC:u11\|LRCK_1X" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "I2C_AV_Config:u10\|WideOr0~38 " "Info: Detected gated clock \"I2C_AV_Config:u10\|WideOr0~38\" as buffer" {  } { { "I2C_AV_Config.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_AV_Config.v" 116 -1 0 } } { "i:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "i:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "I2C_AV_Config:u10\|WideOr0~38" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "I2C_AV_Config:u10\|WideOr0~39 " "Info: Detected gated clock \"I2C_AV_Config:u10\|WideOr0~39\" as buffer" {  } { { "I2C_AV_Config.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_AV_Config.v" 116 -1 0 } } { "i:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "i:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "I2C_AV_Config:u10\|WideOr0~39" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "I2C_AV_Config:u10\|LUT_INDEX\[2\] " "Info: Detected ripple clock \"I2C_AV_Config:u10\|LUT_INDEX\[2\]\" as buffer" {  } { { "I2C_AV_Config.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_AV_Config.v" 75 -1 0 } } { "i:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "i:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "I2C_AV_Config:u10\|LUT_INDEX\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "I2C_AV_Config:u10\|LUT_INDEX\[1\] " "Info: Detected ripple clock \"I2C_AV_Config:u10\|LUT_INDEX\[1\]\" as buffer" {  } { { "I2C_AV_Config.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_AV_Config.v" 75 -1 0 } } { "i:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "i:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "I2C_AV_Config:u10\|LUT_INDEX\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "I2C_AV_Config:u10\|LUT_INDEX\[4\] " "Info: Detected ripple clock \"I2C_AV_Config:u10\|LUT_INDEX\[4\]\" as buffer" {  } { { "I2C_AV_Config.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_AV_Config.v" 75 -1 0 } } { "i:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "i:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "I2C_AV_Config:u10\|LUT_INDEX\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "I2C_AV_Config:u10\|LUT_INDEX\[3\] " "Info: Detected ripple clock \"I2C_AV_Config:u10\|LUT_INDEX\[3\]\" as buffer" {  } { { "I2C_AV_Config.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_AV_Config.v" 75 -1 0 } } { "i:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "i:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "I2C_AV_Config:u10\|LUT_INDEX\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "I2C_AV_Config:u10\|LUT_INDEX\[5\] " "Info: Detected ripple clock \"I2C_AV_Config:u10\|LUT_INDEX\[5\]\" as buffer" {  } { { "I2C_AV_Config.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_AV_Config.v" 75 -1 0 } } { "i:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "i:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "I2C_AV_Config:u10\|LUT_INDEX\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "I2C_AV_Config:u10\|mI2C_CTRL_CLK " "Info: Detected ripple clock \"I2C_AV_Config:u10\|mI2C_CTRL_CLK\" as buffer" {  } { { "I2C_AV_Config.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_AV_Config.v" 16 -1 0 } } { "i:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "i:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "I2C_AV_Config:u10\|mI2C_CTRL_CLK" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "AUDIO_DAC:u11\|LRCK_4X " "Info: Detected ripple clock \"AUDIO_DAC:u11\|LRCK_4X\" as buffer" {  } { { "AUDIO_DAC.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/AUDIO_DAC.v" 74 -1 0 } } { "i:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "i:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "AUDIO_DAC:u11\|LRCK_4X" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "USB_JTAG:u1\|mTCK " "Info: Detected ripple clock \"USB_JTAG:u1\|mTCK\" as buffer" {  } { { "USB_JTAG.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/USB_JTAG.v" 15 -1 0 } } { "i:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "i:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "USB_JTAG:u1\|mTCK" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "Multi_Sdram:u3\|Sdram_Controller:u1\|PLL1:sdram_pll1\|altpll:altpll_component\|_clk0 register Multi_Sdram:u3\|Sdram_Multiplexer:u0\|mSDR_RD register Multi_Sdram:u3\|Sdram_Controller:u1\|Read 8.547 ns " "Info: Slack time is 8.547 ns for clock \"Multi_Sdram:u3\|Sdram_Controller:u1\|PLL1:sdram_pll1\|altpll:altpll_component\|_clk0\" between source register \"Multi_Sdram:u3\|Sdram_Multiplexer:u0\|mSDR_RD\" and destination register \"Multi_Sdram:u3\|Sdram_Controller:u1\|Read\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "16.995 ns + Largest register register " "Info: + Largest register to register requirement is 16.995 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "17.216 ns + " "Info: + Setup relationship between source and destination is 17.216 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 17.216 ns " "Info: + Latch edge is 17.216 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination Multi_Sdram:u3\|Sdram_Controller:u1\|PLL1:sdram_pll1\|altpll:altpll_component\|_clk0 20.000 ns -2.784 ns  50 " "Info: Clock period of Destination clock \"Multi_Sdram:u3\|Sdram_Controller:u1\|PLL1:sdram_pll1\|altpll:altpll_component\|_clk0\" is 20.000 ns with  offset of -2.784 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source OSC_50 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"OSC_50\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.043 ns + Largest " "Info: + Largest clock skew is 0.043 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Multi_Sdram:u3\|Sdram_Controller:u1\|PLL1:sdram_pll1\|altpll:altpll_component\|_clk0 destination 3.244 ns + Shortest register " "Info: + Shortest clock path from clock \"Multi_Sdram:u3\|Sdram_Controller:u1\|PLL1:sdram_pll1\|altpll:altpll_component\|_clk0\" to destination register is 3.244 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Multi_Sdram:u3\|Sdram_Controller:u1\|PLL1:sdram_pll1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'Multi_Sdram:u3\|Sdram_Controller:u1\|PLL1:sdram_pll1\|altpll:altpll_component\|_clk0'" {  } { { "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "i:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.382 ns) + CELL(0.000 ns) 1.382 ns Multi_Sdram:u3\|Sdram_Controller:u1\|PLL1:sdram_pll1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 194 " "Info: 2: + IC(1.382 ns) + CELL(0.000 ns) = 1.382 ns; Loc. = CLKCTRL_G3; Fanout = 194; COMB Node = 'Multi_Sdram:u3\|Sdram_Controller:u1\|PLL1:sdram_pll1\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.382 ns" { Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "i:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.196 ns) + CELL(0.666 ns) 3.244 ns Multi_Sdram:u3\|Sdram_Controller:u1\|Read 3 REG LCFF_X29_Y13_N1 2 " "Info: 3: + IC(1.196 ns) + CELL(0.666 ns) = 3.244 ns; Loc. = LCFF_X29_Y13_N1; Fanout = 2; REG Node = 'Multi_Sdram:u3\|Sdram_Controller:u1\|Read'" {  } { { "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.862 ns" { Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0~clkctrl Multi_Sdram:u3|Sdram_Controller:u1|Read } "NODE_NAME" } } { "Multi_Sdram/Sdram_Controller.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Controller.v" 72 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 20.53 % ) " "Info: Total cell delay = 0.666 ns ( 20.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.578 ns ( 79.47 % ) " "Info: Total interconnect delay = 2.578 ns ( 79.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.244 ns" { Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0~clkctrl Multi_Sdram:u3|Sdram_Controller:u1|Read } "NODE_NAME" } } { "i:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "i:/altera/quartus60/win/Technology_Viewer.qrui" "3.244 ns" { Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0~clkctrl Multi_Sdram:u3|Sdram_Controller:u1|Read } { 0.000ns 1.382ns 1.196ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "OSC_50 source 3.201 ns - Longest register " "Info: - Longest clock path from clock \"OSC_50\" to source register is 3.201 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns OSC_50 1 CLK PIN_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N2; Fanout = 3; CLK Node = 'OSC_50'" {  } { { "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OSC_50 } "NODE_NAME" } } { "DE2_USB_API.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/DE2_USB_API.v" 176 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.349 ns OSC_50~clkctrl 2 COMB CLKCTRL_G2 626 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.349 ns; Loc. = CLKCTRL_G2; Fanout = 626; COMB Node = 'OSC_50~clkctrl'" {  } { { "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.239 ns" { OSC_50 OSC_50~clkctrl } "NODE_NAME" } } { "DE2_USB_API.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/DE2_USB_API.v" 176 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.186 ns) + CELL(0.666 ns) 3.201 ns Multi_Sdram:u3\|Sdram_Multiplexer:u0\|mSDR_RD 3 REG LCFF_X45_Y23_N11 4 " "Info: 3: + IC(1.186 ns) + CELL(0.666 ns) = 3.201 ns; Loc. = LCFF_X45_Y23_N11; Fanout = 4; REG Node = 'Multi_Sdram:u3\|Sdram_Multiplexer:u0\|mSDR_RD'" {  } { { "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.852 ns" { OSC_50~clkctrl Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_RD } "NODE_NAME" } } { "Multi_Sdram/Sdram_Multiplexer.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Multiplexer.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.776 ns ( 55.48 % ) " "Info: Total cell delay = 1.776 ns ( 55.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.425 ns ( 44.52 % ) " "Info: Total interconnect delay = 1.425 ns ( 44.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.201 ns" { OSC_50 OSC_50~clkctrl Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_RD } "NODE_NAME" } } { "i:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "i:/altera/quartus60/win/Technology_Viewer.qrui" "3.201 ns" { OSC_50 OSC_50~combout OSC_50~clkctrl Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_RD } { 0.000ns 0.000ns 0.239ns 1.186ns } { 0.000ns 1.110ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.244 ns" { Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0~clkctrl Multi_Sdram:u3|Sdram_Controller:u1|Read } "NODE_NAME" } } { "i:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "i:/altera/quartus60/win/Technology_Viewer.qrui" "3.244 ns" { Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0~clkctrl Multi_Sdram:u3|Sdram_Controller:u1|Read } { 0.000ns 1.382ns 1.196ns } { 0.000ns 0.000ns 0.666ns } } } { "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.201 ns" { OSC_50 OSC_50~clkctrl Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_RD } "NODE_NAME" } } { "i:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "i:/altera/quartus60/win/Technology_Viewer.qrui" "3.201 ns" { OSC_50 OSC_50~combout OSC_50~clkctrl Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_RD } { 0.000ns 0.000ns 0.239ns 1.186ns } { 0.000ns 1.110ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "Multi_Sdram/Sdram_Multiplexer.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Multiplexer.v" 49 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns - " "Info: - Micro setup delay of destination is -0.040 ns" {  } { { "Multi_Sdram/Sdram_Controller.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Controller.v" 72 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.244 ns" { Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0~clkctrl Multi_Sdram:u3|Sdram_Controller:u1|Read } "NODE_NAME" } } { "i:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "i:/altera/quartus60/win/Technology_Viewer.qrui" "3.244 ns" { Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0~clkctrl Multi_Sdram:u3|Sdram_Controller:u1|Read } { 0.000ns 1.382ns 1.196ns } { 0.000ns 0.000ns 0.666ns } } } { "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.201 ns" { OSC_50 OSC_50~clkctrl Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_RD } "NODE_NAME" } } { "i:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "i:/altera/quartus60/win/Technology_Viewer.qrui" "3.201 ns" { OSC_50 OSC_50~combout OSC_50~clkctrl Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_RD } { 0.000ns 0.000ns 0.239ns 1.186ns } { 0.000ns 1.110ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.448 ns - Longest register register " "Info: - Longest register to register delay is 8.448 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Multi_Sdram:u3\|Sdram_Multiplexer:u0\|mSDR_RD 1 REG LCFF_X45_Y23_N11 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X45_Y23_N11; Fanout = 4; REG Node = 'Multi_Sdram:u3\|Sdram_Multiplexer:u0\|mSDR_RD'" {  } { { "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_RD } "NODE_NAME" } } { "Multi_Sdram/Sdram_Multiplexer.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Multiplexer.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.843 ns) + CELL(0.206 ns) 3.049 ns Multi_Sdram:u3\|Sdram_Multiplexer:u0\|oSDR_RD~53 2 COMB LCCOMB_X29_Y13_N2 20 " "Info: 2: + IC(2.843 ns) + CELL(0.206 ns) = 3.049 ns; Loc. = LCCOMB_X29_Y13_N2; Fanout = 20; COMB Node = 'Multi_Sdram:u3\|Sdram_Multiplexer:u0\|oSDR_RD~53'" {  } { { "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.049 ns" { Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_RD Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_RD~53 } "NODE_NAME" } } { "Multi_Sdram/Sdram_Multiplexer.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Multiplexer.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.052 ns) + CELL(0.206 ns) 4.307 ns Multi_Sdram:u3\|Sdram_Controller:u1\|Equal1~49 3 COMB LCCOMB_X29_Y13_N12 3 " "Info: 3: + IC(1.052 ns) + CELL(0.206 ns) = 4.307 ns; Loc. = LCCOMB_X29_Y13_N12; Fanout = 3; COMB Node = 'Multi_Sdram:u3\|Sdram_Controller:u1\|Equal1~49'" {  } { { "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.258 ns" { Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_RD~53 Multi_Sdram:u3|Sdram_Controller:u1|Equal1~49 } "NODE_NAME" } } { "Multi_Sdram/Sdram_Controller.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Controller.v" 203 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.148 ns) + CELL(0.651 ns) 6.106 ns Multi_Sdram:u3\|Sdram_Controller:u1\|Read~350 4 COMB LCCOMB_X29_Y13_N8 2 " "Info: 4: + IC(1.148 ns) + CELL(0.651 ns) = 6.106 ns; Loc. = LCCOMB_X29_Y13_N8; Fanout = 2; COMB Node = 'Multi_Sdram:u3\|Sdram_Controller:u1\|Read~350'" {  } { { "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.799 ns" { Multi_Sdram:u3|Sdram_Controller:u1|Equal1~49 Multi_Sdram:u3|Sdram_Controller:u1|Read~350 } "NODE_NAME" } } { "Multi_Sdram/Sdram_Controller.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Controller.v" 72 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.583 ns) + CELL(0.651 ns) 8.340 ns Multi_Sdram:u3\|Sdram_Controller:u1\|Read~349 5 COMB LCCOMB_X29_Y13_N0 1 " "Info: 5: + IC(1.583 ns) + CELL(0.651 ns) = 8.340 ns; Loc. = LCCOMB_X29_Y13_N0; Fanout = 1; COMB Node = 'Multi_Sdram:u3\|Sdram_Controller:u1\|Read~349'" {  } { { "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.234 ns" { Multi_Sdram:u3|Sdram_Controller:u1|Read~350 Multi_Sdram:u3|Sdram_Controller:u1|Read~349 } "NODE_NAME" } } { "Multi_Sdram/Sdram_Controller.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Controller.v" 72 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.448 ns Multi_Sdram:u3\|Sdram_Controller:u1\|Read 6 REG LCFF_X29_Y13_N1 2 " "Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 8.448 ns; Loc. = LCFF_X29_Y13_N1; Fanout = 2; REG Node = 'Multi_Sdram:u3\|Sdram_Controller:u1\|Read'" {  } { { "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { Multi_Sdram:u3|Sdram_Controller:u1|Read~349 Multi_Sdram:u3|Sdram_Controller:u1|Read } "NODE_NAME" } } { "Multi_Sdram/Sdram_Controller.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Controller.v" 72 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.822 ns ( 21.57 % ) " "Info: Total cell delay = 1.822 ns ( 21.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.626 ns ( 78.43 % ) " "Info: Total interconnect delay = 6.626 ns ( 78.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.448 ns" { Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_RD Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_RD~53 Multi_Sdram:u3|Sdram_Controller:u1|Equal1~49 Multi_Sdram:u3|Sdram_Controller:u1|Read~350 Multi_Sdram:u3|Sdram_Controller:u1|Read~349 Multi_Sdram:u3|Sdram_Controller:u1|Read } "NODE_NAME" } } { "i:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "i:/altera/quartus60/win/Technology_Viewer.qrui" "8.448 ns" { Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_RD Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_RD~53 Multi_Sdram:u3|Sdram_Controller:u1|Equal1~49 Multi_Sdram:u3|Sdram_Controller:u1|Read~350 Multi_Sdram:u3|Sdram_Controller:u1|Read~349 Multi_Sdram:u3|Sdram_Controller:u1|Read } { 0.000ns 2.843ns 1.052ns 1.148ns 1.583ns 0.000ns } { 0.000ns 0.206ns 0.206ns 0.651ns 0.651ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.244 ns" { Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0~clkctrl Multi_Sdram:u3|Sdram_Controller:u1|Read } "NODE_NAME" } } { "i:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "i:/altera/quartus60/win/Technology_Viewer.qrui" "3.244 ns" { Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0~clkctrl Multi_Sdram:u3|Sdram_Controller:u1|Read } { 0.000ns 1.382ns 1.196ns } { 0.000ns 0.000ns 0.666ns } } } { "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.201 ns" { OSC_50 OSC_50~clkctrl Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_RD } "NODE_NAME" } } { "i:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "i:/altera/quartus60/win/Technology_Viewer.qrui" "3.201 ns" { OSC_50 OSC_50~combout OSC_50~clkctrl Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_RD } { 0.000ns 0.000ns 0.239ns 1.186ns } { 0.000ns 1.110ns 0.000ns 0.666ns } } } { "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.448 ns" { Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_RD Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_RD~53 Multi_Sdram:u3|Sdram_Controller:u1|Equal1~49 Multi_Sdram:u3|Sdram_Controller:u1|Read~350 Multi_Sdram:u3|Sdram_Controller:u1|Read~349 Multi_Sdram:u3|Sdram_Controller:u1|Read } "NODE_NAME" } } { "i:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "i:/altera/quartus60/win/Technology_Viewer.qrui" "8.448 ns" { Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_RD Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_RD~53 Multi_Sdram:u3|Sdram_Controller:u1|Equal1~49 Multi_Sdram:u3|Sdram_Controller:u1|Read~350 Multi_Sdram:u3|Sdram_Controller:u1|Read~349 Multi_Sdram:u3|Sdram_Controller:u1|Read } { 0.000ns 2.843ns 1.052ns 1.148ns 1.583ns 0.000ns } { 0.000ns 0.206ns 0.206ns 0.651ns 0.651ns 0.108ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}