de2_usb_api.tan.qmsg

Altera de2开发板提供的配套软件程序

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "I2C_AV_Config:u10\|LUT_DATA\[1\] " "Warning: Node \"I2C_AV_Config:u10\|LUT_DATA\[1\]\" is a latch" {  } { { "I2C_AV_Config.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_AV_Config.v" 116 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "I2C_AV_Config:u10\|LUT_DATA\[12\] " "Warning: Node \"I2C_AV_Config:u10\|LUT_DATA\[12\]\" is a latch" {  } { { "I2C_AV_Config.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_AV_Config.v" 116 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "I2C_AV_Config:u10\|LUT_DATA\[5\] " "Warning: Node \"I2C_AV_Config:u10\|LUT_DATA\[5\]\" is a latch" {  } { { "I2C_AV_Config.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_AV_Config.v" 116 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "I2C_AV_Config:u10\|LUT_DATA\[6\] " "Warning: Node \"I2C_AV_Config:u10\|LUT_DATA\[6\]\" is a latch" {  } { { "I2C_AV_Config.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_AV_Config.v" 116 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "I2C_AV_Config:u10\|LUT_DATA\[7\] " "Warning: Node \"I2C_AV_Config:u10\|LUT_DATA\[7\]\" is a latch" {  } { { "I2C_AV_Config.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_AV_Config.v" 116 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "I2C_AV_Config:u10\|LUT_DATA\[0\] " "Warning: Node \"I2C_AV_Config:u10\|LUT_DATA\[0\]\" is a latch" {  } { { "I2C_AV_Config.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_AV_Config.v" 116 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "I2C_AV_Config:u10\|LUT_DATA\[3\] " "Warning: Node \"I2C_AV_Config:u10\|LUT_DATA\[3\]\" is a latch" {  } { { "I2C_AV_Config.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_AV_Config.v" 116 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "I2C_AV_Config:u10\|LUT_DATA\[2\] " "Warning: Node \"I2C_AV_Config:u10\|LUT_DATA\[2\]\" is a latch" {  } { { "I2C_AV_Config.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_AV_Config.v" 116 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "I2C_AV_Config:u10\|LUT_DATA\[9\] " "Warning: Node \"I2C_AV_Config:u10\|LUT_DATA\[9\]\" is a latch" {  } { { "I2C_AV_Config.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_AV_Config.v" 116 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "I2C_AV_Config:u10\|LUT_DATA\[14\] " "Warning: Node \"I2C_AV_Config:u10\|LUT_DATA\[14\]\" is a latch" {  } { { "I2C_AV_Config.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_AV_Config.v" 116 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "I2C_AV_Config:u10\|LUT_DATA\[13\] " "Warning: Node \"I2C_AV_Config:u10\|LUT_DATA\[13\]\" is a latch" {  } { { "I2C_AV_Config.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_AV_Config.v" 116 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "I2C_AV_Config:u10\|LUT_DATA\[10\] " "Warning: Node \"I2C_AV_Config:u10\|LUT_DATA\[10\]\" is a latch" {  } { { "I2C_AV_Config.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_AV_Config.v" 116 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "I2C_AV_Config:u10\|LUT_DATA\[11\] " "Warning: Node \"I2C_AV_Config:u10\|LUT_DATA\[11\]\" is a latch" {  } { { "I2C_AV_Config.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_AV_Config.v" 116 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "I2C_AV_Config:u10\|LUT_DATA\[8\] " "Warning: Node \"I2C_AV_Config:u10\|LUT_DATA\[8\]\" is a latch" {  } { { "I2C_AV_Config.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_AV_Config.v" 116 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "I2C_AV_Config:u10\|LUT_DATA\[15\] " "Warning: Node \"I2C_AV_Config:u10\|LUT_DATA\[15\]\" is a latch" {  } { { "I2C_AV_Config.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_AV_Config.v" 116 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "I2C_AV_Config:u10\|LUT_DATA\[4\] " "Warning: Node \"I2C_AV_Config:u10\|LUT_DATA\[4\]\" is a latch" {  } { { "I2C_AV_Config.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_AV_Config.v" 116 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" {  } {  } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "TCK " "Info: Assuming node \"TCK\" is an undefined clock" {  } { { "DE2_USB_API.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/DE2_USB_API.v" 263 -1 0 } } { "i:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "i:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "TCK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}