de2_usb_api.hif

Altera de2开发板提供的配套软件程序

USR
PORT_CLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK1
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATAOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ACTIVECLOCK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKLOSS
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_FBIN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PLLENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKSWITCH
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ARESET
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_PFDENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANACLR
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANREAD
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANWRITE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_LOCKED
PORT_UNUSED
PARAMETER_UNKNOWN
USR
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
inclk
-1
3
clk
-1
3
areset
-1
3
scanwrite
-1
1
scanread
-1
1
scandata
-1
1
scanclk
-1
1
scanaclr
-1
1
clkswitch
-1
1
pllena
-1
2
pfdena
-1
2
fbin
-1
2
extclkena
-1
2
clkena
-1
2
}
# include_file {
i:|altera|quartus60|libraries|megafunctions|stratix_pll.inc
5f8211898149ceae8264a0ea5036254f
i:|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
i:|altera|quartus60|libraries|megafunctions|stratixii_pll.inc
6d1985e16ab5f59a1fd6b0ae20978a4e
i:|altera|quartus60|libraries|megafunctions|cycloneii_pll.inc
39a0d9d1237d1db39c848c3f9faffc
}
# hierarchies {
VGA_Audio_PLL:p1|altpll:altpll_component
}
# end
# entity
VGA_Controller
# storage
db|DE2_USB_API.(26).cnf
db|DE2_USB_API.(26).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
VGA_Controller|VGA_Controller.v
b3b9c0d8fe69ca23d30ab33cf629f19
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
H_SYNC_CYC
96
PARAMETER_DEC
DEF
H_SYNC_BACK
48
PARAMETER_DEC
DEF
H_SYNC_ACT
640
PARAMETER_DEC
DEF
H_SYNC_FRONT
16
PARAMETER_DEC
DEF
H_SYNC_TOTAL
800
PARAMETER_DEC
DEF
V_SYNC_CYC
2
PARAMETER_DEC
DEF
V_SYNC_BACK
32
PARAMETER_DEC
DEF
V_SYNC_ACT
480
PARAMETER_DEC
DEF
V_SYNC_FRONT
11
PARAMETER_DEC
DEF
V_SYNC_TOTAL
525
PARAMETER_DEC
DEF
X_START
148
PARAMETER_DEC
DEF
Y_START
34
PARAMETER_DEC
DEF
}
# include_file {
VGA_Controller|VGA_Param.h
22d76eff94710ac26d957dd18618e6
}
# hierarchies {
VGA_Controller:u8
}
# end
# entity
VGA_OSD_RAM
# storage
db|DE2_USB_API.(27).cnf
db|DE2_USB_API.(27).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
VGA_Controller|VGA_OSD_RAM.v
d13343d83cd650e7132656823fef1d64
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
VGA_OSD_RAM:u9
}
# end
# entity
Img_RAM
# storage
db|DE2_USB_API.(28).cnf
db|DE2_USB_API.(28).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
VGA_Controller|Img_RAM.v
7e8929c8261b40350b3794a631bd3da
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
VGA_OSD_RAM:u9|Img_RAM:u0
}
# end
# entity
altsyncram
# storage
db|DE2_USB_API.(29).cnf
db|DE2_USB_API.(29).cnf
# case_insensitive
# source_file
i:|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
1
PARAMETER_DEC
USR
WIDTHAD_A
19
PARAMETER_DEC
USR
NUMWORDS_A
307200
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
8
PARAMETER_DEC
USR
WIDTHAD_B
16
PARAMETER_DEC
USR
NUMWORDS_B
38400
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
M4K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
Img_DATA.hex
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_B
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
BYPASS
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_q7o1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b
-1
3
data_a
-1
3
clock1
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# include_file {
i:|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
i:|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
i:|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
i:|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
i:|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
i:|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
i:|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
i:|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
i:|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
i:|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
}
# hierarchies {
VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_q7o1
# storage
db|DE2_USB_API.(30).cnf
db|DE2_USB_API.(30).cnf
# case_insensitive
# source_file
db|altsyncram_q7o1.tdf
4c40a7102dcce07eec512931a1a1606e
6
# used_port {
wren_a
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a0
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b15
-1
3
address_b14
-1
3
address_b13
-1
3
address_b12
-1
3
address_b11
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a18
-1
3
address_a17
-1
3
address_a16
-1
3
address_a15
-1
3
address_a14
-1
3
address_a13
-1
3
address_a12
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_q7o1:auto_generated
}
# end
# entity
altsyncram_p132
# storage
db|DE2_USB_API.(31).cnf
db|DE2_USB_API.(31).cnf
# case_insensitive
# source_file
db|altsyncram_p132.tdf
de95a77cac46e711b16ce31fb7ef3af
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_b
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
data_b0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b18
-1
3
address_b17
-1
3
address_b16
-1
3
address_b15
-1
3
address_b14
-1
3
address_b13
-1
3
address_b12
-1
3
address_b11
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a15
-1
3
address_a14
-1
3
address_a13
-1
3
address_a12
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
wren_a
-1
1
data_a7
-1
2
data_a6
-1
2
data_a5
-1
2
data_a4
-1
2
data_a3
-1
2
data_a2
-1
2
data_a1
-1
2
data_a0
-1
2
}
# memory_file {
Img_DATA.hex
3e4a986147a9b27bd5613aedddd34a0
}
# hierarchies {
VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_q7o1:auto_generated|altsyncram_p132:altsyncram1
}
# end
# entity
decode_1qa
# storage
db|DE2_USB_API.(32).cnf
db|DE2_USB_API.(32).cnf
# case_insensitive
# source_file
db|decode_1qa.tdf
dfe40df6ecd32fcdc25ea4464e872ae
6
# used_port {
eq9
-1
3
eq8
-1
3
eq74
-1
3
eq73
-1
3
eq72
-1
3
eq71
-1
3
eq70
-1
3
eq7
-1
3
eq69
-1
3
eq68
-1
3
eq67
-1
3
eq66
-1
3
eq65
-1
3
eq64
-1
3
eq63
-1
3
eq62
-1
3
eq61
-1
3
eq60
-1
3
eq6
-1
3
eq59
-1
3
eq58
-1
3
eq57
-1
3
eq56
-1
3
eq55
-1
3
eq54
-1
3
eq53
-1
3
eq52
-1
3
eq51
-1
3
eq50
-1
3
eq5
-1
3
eq49
-1
3
eq48
-1
3
eq47
-1
3
eq46
-1
3
eq45
-1
3
eq44
-1
3
eq43
-1
3
eq42
-1
3
eq41
-1
3
eq40
-1
3
eq4
-1
3
eq39
-1
3
eq38
-1
3
eq37
-1
3
eq36
-1
3
eq35
-1
3
eq34
-1
3
eq33
-1
3
eq32
-1
3
eq31
-1
3
eq30
-1
3
eq3
-1
3
eq29
-1
3
eq28
-1
3
eq27
-1
3
eq26
-1
3
eq25
-1
3
eq24
-1
3
eq23
-1
3
eq22
-1
3
eq21
-1
3
eq20
-1
3
eq2
-1
3
eq19
-1
3
eq18
-1
3
eq17
-1
3
eq16
-1
3
eq15
-1
3
eq14
-1
3
eq13
-1
3
eq12
-1
3
eq11
-1
3
eq10
-1
3
eq1
-1
3
eq0
-1
3
enable
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_q7o1:auto_generated|altsyncram_p132:altsyncram1|decode_1qa:decode3
VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_q7o1:auto_generated|altsyncram_p132:altsyncram1|decode_1qa:decode4
}
# end
# entity
decode_1qa
# storage
db|DE2_USB_API.(33).cnf
db|DE2_USB_API.(33).cnf
# case_insensitive
# source_file
db|decode_1qa.tdf
dfe40df6ecd32fcdc25ea4464e872ae
6
# used_port {
eq9
-1
3
eq8
-1
3
eq74
-1
3
eq73
-1
3
eq72
-1
3
eq71
-1
3
eq70
-1
3
eq7
-1
3
eq69
-1
3
eq68
-1
3
eq67
-1
3
eq66
-1
3
eq65
-1
3
eq64
-1
3
eq63
-1
3
eq62
-1
3
eq61
-1
3
eq60
-1
3
eq6
-1
3
eq59
-1
3
eq58
-1
3
eq57
-1
3
eq56
-1
3
eq55
-1
3
eq54
-1
3
eq53
-1
3
eq52
-1
3
eq51
-1
3
eq50
-1
3
eq5
-1
3
eq49
-1
3
eq48
-1
3
eq47
-1
3