de2_usb_api.fit.qmsg

Altera de2开发板提供的配套软件程序

{ "Info" "IMPP_MPP_USER_DEVICE" "DE2_USB_API EP2C35F672C8 " "Info: Selected device EP2C35F672C8 for design \"DE2_USB_API\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "Multi_Sdram:u3\|Sdram_Controller:u1\|PLL1:sdram_pll1\|altpll:altpll_component\|pll Cyclone II " "Info: Implemented PLL \"Multi_Sdram:u3\|Sdram_Controller:u1\|PLL1:sdram_pll1\|altpll:altpll_component\|pll\" as Cyclone II PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "Multi_Sdram:u3\|Sdram_Controller:u1\|PLL1:sdram_pll1\|altpll:altpll_component\|_clk0 1 1 0 0 " "Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for Multi_Sdram:u3\|Sdram_Controller:u1\|PLL1:sdram_pll1\|altpll:altpll_component\|_clk0 port" {  } { { "altpll.tdf" "" { Text "i:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "Multi_Sdram:u3\|Sdram_Controller:u1\|PLL1:sdram_pll1\|altpll:altpll_component\|_clk2 1 1 0 0 " "Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for Multi_Sdram:u3\|Sdram_Controller:u1\|PLL1:sdram_pll1\|altpll:altpll_component\|_clk2 port" {  } { { "altpll.tdf" "" { Text "i:/altera/quartus60/libraries/megafunctions/altpll.tdf" 761 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0}  } { { "altpll.tdf" "" { Text "i:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "Implemented PLL \"%1!s!\" as %2!s! PLL type" 0 0}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "VGA_Audio_PLL:p1\|altpll:altpll_component\|pll Cyclone II " "Info: Implemented PLL \"VGA_Audio_PLL:p1\|altpll:altpll_component\|pll\" as Cyclone II PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 14 15 0 0 " "Info: Implementing clock multiplication of 14, clock division of 15, and phase shift of 0 degrees (0 ps) for VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 port" {  } { { "altpll.tdf" "" { Text "i:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1 2 3 0 0 " "Info: Implementing clock multiplication of 2, clock division of 3, and phase shift of 0 degrees (0 ps) for VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1 port" {  } { { "altpll.tdf" "" { Text "i:/altera/quartus60/libraries/megafunctions/altpll.tdf" 764 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0}  } { { "altpll.tdf" "" { Text "i:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "Implemented PLL \"%1!s!\" as %2!s! PLL type" 0 0}