de2_usb_api.hier_info

Altera de2开发板提供的配套软件程序

iFL_Ready => oHS_Ready~0.DATAB
iFL_Ready => mFL_Start~0.OUTPUTSELECT
iFL_Ready => ST~0.OUTPUTSELECT
iFL_Ready => ST~1.OUTPUTSELECT
iFL_Ready => ST~2.OUTPUTSELECT
iFL_Ready => ST~3.OUTPUTSELECT
oFL_Start <= oFL_Start~0.DB_MAX_OUTPUT_PORT_TYPE
iSelect[0] => Equal0.IN31
iSelect[0] => Equal1.IN61
iSelect[0] => Equal2.IN30
iSelect[0] => Equal3.IN61
iSelect[1] => Equal0.IN30
iSelect[1] => Equal1.IN30
iSelect[1] => Equal2.IN61
iSelect[1] => Equal3.IN60
iCLK => mFL_DATA[6].CLK
iCLK => mFL_DATA[5].CLK
iCLK => mFL_DATA[4].CLK
iCLK => mFL_DATA[3].CLK
iCLK => mFL_DATA[2].CLK
iCLK => mFL_DATA[1].CLK
iCLK => mFL_DATA[0].CLK
iCLK => mFL_Start.CLK
iCLK => mFL_DATA[7].CLK
iCLK => ST~11.IN1
iRST_n => mFL_DATA[6].ACLR
iRST_n => mFL_DATA[5].ACLR
iRST_n => mFL_DATA[4].ACLR
iRST_n => mFL_DATA[3].ACLR
iRST_n => mFL_DATA[2].ACLR
iRST_n => mFL_DATA[1].ACLR
iRST_n => mFL_DATA[0].ACLR
iRST_n => mFL_Start.ACLR
iRST_n => mFL_DATA[7].ACLR
iRST_n => ST~12.IN1


|DE2_USB_API|Multi_Flash:u2|Flash_Controller:u1
oDATA[0] <= oDATA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oDATA[1] <= oDATA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oDATA[2] <= oDATA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oDATA[3] <= oDATA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oDATA[4] <= oDATA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oDATA[5] <= oDATA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oDATA[6] <= oDATA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oDATA[7] <= oDATA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
iDATA[0] => r_DATA[0].DATAIN
iDATA[1] => r_DATA[1].DATAIN
iDATA[2] => r_DATA[2].DATAIN
iDATA[3] => r_DATA[3].DATAIN
iDATA[4] => r_DATA[4].DATAIN
iDATA[5] => r_DATA[5].DATAIN
iDATA[6] => r_DATA[6].DATAIN
iDATA[7] => r_DATA[7].DATAIN
iADDR[0] => r_ADDR[0].DATAIN
iADDR[1] => r_ADDR[1].DATAIN
iADDR[2] => r_ADDR[2].DATAIN
iADDR[3] => r_ADDR[3].DATAIN
iADDR[4] => r_ADDR[4].DATAIN
iADDR[5] => r_ADDR[5].DATAIN
iADDR[6] => r_ADDR[6].DATAIN
iADDR[7] => r_ADDR[7].DATAIN
iADDR[8] => r_ADDR[8].DATAIN
iADDR[9] => r_ADDR[9].DATAIN
iADDR[10] => r_ADDR[10].DATAIN
iADDR[11] => r_ADDR[11].DATAIN
iADDR[12] => r_ADDR[12].DATAIN
iADDR[13] => r_ADDR[13].DATAIN
iADDR[14] => r_ADDR[14].DATAIN
iADDR[15] => r_ADDR[15].DATAIN
iADDR[16] => r_ADDR[16].DATAIN
iADDR[17] => r_ADDR[17].DATAIN
iADDR[18] => r_ADDR[18].DATAIN
iADDR[19] => r_ADDR[19].DATAIN
iADDR[20] => r_ADDR[20].DATAIN
iADDR[21] => r_ADDR[21].DATAIN
iCMD[0] => r_CMD[0].DATAIN
iCMD[1] => r_CMD[1].DATAIN
iCMD[2] => r_CMD[2].DATAIN
oReady <= oReady~0.DB_MAX_OUTPUT_PORT_TYPE
iStart => preStart.DATAIN
iStart => Equal1.IN1
iCLK => Cont_DIV[9].CLK
iCLK => Cont_DIV[8].CLK
iCLK => Cont_DIV[7].CLK
iCLK => Cont_DIV[6].CLK
iCLK => Cont_DIV[5].CLK
iCLK => Cont_DIV[4].CLK
iCLK => Cont_DIV[3].CLK
iCLK => Cont_DIV[2].CLK
iCLK => Cont_DIV[1].CLK
iCLK => Cont_DIV[0].CLK
iCLK => mCLK.CLK
iCLK => WE_CLK_Delay[4].CLK
iCLK => WE_CLK_Delay[3].CLK
iCLK => WE_CLK_Delay[2].CLK
iCLK => WE_CLK_Delay[1].CLK
iCLK => WE_CLK_Delay[0].CLK
iCLK => mStart.CLK
iCLK => Start_Delay[10].CLK
iCLK => Start_Delay[9].CLK
iCLK => Start_Delay[8].CLK
iCLK => Start_Delay[7].CLK
iCLK => Start_Delay[6].CLK
iCLK => Start_Delay[5].CLK
iCLK => Start_Delay[4].CLK
iCLK => Start_Delay[3].CLK
iCLK => Start_Delay[2].CLK
iCLK => Start_Delay[1].CLK
iCLK => Start_Delay[0].CLK
iCLK => preStart.CLK
iCLK => pre_mCLK.CLK
iCLK => mACT.CLK
iCLK => r_CMD[2].CLK
iCLK => r_CMD[1].CLK
iCLK => r_CMD[0].CLK
iCLK => r_ADDR[21].CLK
iCLK => r_ADDR[20].CLK
iCLK => r_ADDR[19].CLK
iCLK => r_ADDR[18].CLK
iCLK => r_ADDR[17].CLK
iCLK => r_ADDR[16].CLK
iCLK => r_ADDR[15].CLK
iCLK => r_ADDR[14].CLK
iCLK => r_ADDR[13].CLK
iCLK => r_ADDR[12].CLK
iCLK => r_ADDR[11].CLK
iCLK => r_ADDR[10].CLK
iCLK => r_ADDR[9].CLK
iCLK => r_ADDR[8].CLK
iCLK => r_ADDR[7].CLK
iCLK => r_ADDR[6].CLK
iCLK => r_ADDR[5].CLK
iCLK => r_ADDR[4].CLK
iCLK => r_ADDR[3].CLK
iCLK => r_ADDR[2].CLK
iCLK => r_ADDR[1].CLK
iCLK => r_ADDR[0].CLK
iCLK => r_DATA[7].CLK
iCLK => r_DATA[6].CLK
iCLK => r_DATA[5].CLK
iCLK => r_DATA[4].CLK
iCLK => r_DATA[3].CLK
iCLK => r_DATA[2].CLK
iCLK => r_DATA[1].CLK
iCLK => r_DATA[0].CLK
iCLK => oDATA[7]~reg0.CLK
iCLK => oDATA[6]~reg0.CLK
iCLK => oDATA[5]~reg0.CLK
iCLK => oDATA[4]~reg0.CLK
iCLK => oDATA[3]~reg0.CLK
iCLK => oDATA[2]~reg0.CLK
iCLK => oDATA[1]~reg0.CLK
iCLK => oDATA[0]~reg0.CLK
iCLK => mFinish.CLK
iCLK => Cont_Finish[21].CLK
iCLK => Cont_Finish[20].CLK
iCLK => Cont_Finish[19].CLK
iCLK => Cont_Finish[18].CLK
iCLK => Cont_Finish[17].CLK
iCLK => Cont_Finish[16].CLK
iCLK => Cont_Finish[15].CLK
iCLK => Cont_Finish[14].CLK
iCLK => Cont_Finish[13].CLK
iCLK => Cont_Finish[12].CLK
iCLK => Cont_Finish[11].CLK
iCLK => Cont_Finish[10].CLK
iCLK => Cont_Finish[9].CLK
iCLK => Cont_Finish[8].CLK
iCLK => Cont_Finish[7].CLK
iCLK => Cont_Finish[6].CLK
iCLK => Cont_Finish[5].CLK
iCLK => Cont_Finish[4].CLK
iCLK => Cont_Finish[3].CLK
iCLK => Cont_Finish[2].CLK
iCLK => Cont_Finish[1].CLK
iCLK => Cont_Finish[0].CLK
iCLK => CMD_Period[21].CLK
iCLK => CMD_Period[20].CLK
iCLK => CMD_Period[19].CLK
iCLK => CMD_Period[18].CLK
iCLK => CMD_Period[17].CLK
iCLK => CMD_Period[16].CLK
iCLK => CMD_Period[15].CLK
iCLK => CMD_Period[14].CLK
iCLK => CMD_Period[13].CLK
iCLK => CMD_Period[12].CLK
iCLK => CMD_Period[11].CLK
iCLK => CMD_Period[10].CLK
iCLK => CMD_Period[9].CLK
iCLK => CMD_Period[8].CLK
iCLK => CMD_Period[7].CLK
iCLK => CMD_Period[6].CLK
iCLK => CMD_Period[5].CLK
iCLK => CMD_Period[4].CLK
iCLK => CMD_Period[3].CLK
iCLK => CMD_Period[2].CLK
iCLK => CMD_Period[1].CLK
iCLK => CMD_Period[0].CLK
iCLK => Cont_DIV[10].CLK
iCLK => ST~61.IN1
iRST_n => Start_Delay[10].ACLR
iRST_n => Start_Delay[9].ACLR
iRST_n => Start_Delay[8].ACLR
iRST_n => Start_Delay[7].ACLR
iRST_n => Start_Delay[6].ACLR
iRST_n => Start_Delay[5].ACLR
iRST_n => Start_Delay[4].ACLR
iRST_n => Start_Delay[3].ACLR
iRST_n => Start_Delay[2].ACLR
iRST_n => Start_Delay[1].ACLR
iRST_n => Start_Delay[0].ACLR
iRST_n => preStart.ACLR
iRST_n => pre_mCLK.ACLR
iRST_n => mACT.ACLR
iRST_n => Cont_DIV[9].ACLR
iRST_n => mStart.ACLR
iRST_n => Cont_DIV[8].ACLR
iRST_n => Cont_DIV[7].ACLR
iRST_n => Cont_DIV[6].ACLR
iRST_n => Cont_DIV[5].ACLR
iRST_n => Cont_DIV[4].ACLR
iRST_n => Cont_DIV[3].ACLR
iRST_n => Cont_DIV[2].ACLR
iRST_n => Cont_DIV[1].ACLR
iRST_n => Cont_DIV[0].ACLR
iRST_n => mCLK.ACLR
iRST_n => oDATA[6]~reg0.ACLR
iRST_n => Cont_DIV[10].ACLR
iRST_n => oDATA[5]~reg0.ACLR
iRST_n => oDATA[4]~reg0.ACLR
iRST_n => oDATA[3]~reg0.ACLR
iRST_n => oDATA[2]~reg0.ACLR
iRST_n => oDATA[1]~reg0.ACLR
iRST_n => oDATA[0]~reg0.ACLR
iRST_n => oDATA[7]~reg0.ACLR
iRST_n => WE_CLK_Delay[4].ACLR
iRST_n => WE_CLK_Delay[3].ACLR
iRST_n => WE_CLK_Delay[2].ACLR
iRST_n => WE_CLK_Delay[1].ACLR
iRST_n => WE_CLK_Delay[0].ACLR
iRST_n => Cont_Finish[21].ACLR
iRST_n => Cont_Finish[20].ACLR
iRST_n => Cont_Finish[19].ACLR
iRST_n => Cont_Finish[18].ACLR
iRST_n => Cont_Finish[17].ACLR
iRST_n => Cont_Finish[16].ACLR
iRST_n => Cont_Finish[15].ACLR
iRST_n => Cont_Finish[14].ACLR
iRST_n => Cont_Finish[13].ACLR
iRST_n => Cont_Finish[12].ACLR
iRST_n => Cont_Finish[11].ACLR
iRST_n => Cont_Finish[10].ACLR
iRST_n => Cont_Finish[9].ACLR
iRST_n => Cont_Finish[8].ACLR
iRST_n => Cont_Finish[7].ACLR
iRST_n => Cont_Finish[6].ACLR
iRST_n => Cont_Finish[5].ACLR
iRST_n => Cont_Finish[4].ACLR
iRST_n => Cont_Finish[3].ACLR
iRST_n => Cont_Finish[2].ACLR
iRST_n => Cont_Finish[1].ACLR
iRST_n => Cont_Finish[0].ACLR
iRST_n => mFinish.ACLR
iRST_n => ST~62.IN1
FL_DQ[0] <= FL_DQ~15
FL_DQ[1] <= FL_DQ~14
FL_DQ[2] <= FL_DQ~13
FL_DQ[3] <= FL_DQ~12
FL_DQ[4] <= FL_DQ~11
FL_DQ[5] <= FL_DQ~10
FL_DQ[6] <= FL_DQ~9
FL_DQ[7] <= FL_DQ~8
FL_ADDR[0] <= Selector52.DB_MAX_OUTPUT_PORT_TYPE
FL_ADDR[1] <= Selector51.DB_MAX_OUTPUT_PORT_TYPE
FL_ADDR[2] <= Selector50.DB_MAX_OUTPUT_PORT_TYPE
FL_ADDR[3] <= Selector49.DB_MAX_OUTPUT_PORT_TYPE
FL_ADDR[4] <= Selector48.DB_MAX_OUTPUT_PORT_TYPE
FL_ADDR[5] <= Selector47.DB_MAX_OUTPUT_PORT_TYPE
FL_ADDR[6] <= Selector46.DB_MAX_OUTPUT_PORT_TYPE
FL_ADDR[7] <= Selector45.DB_MAX_OUTPUT_PORT_TYPE
FL_ADDR[8] <= Selector44.DB_MAX_OUTPUT_PORT_TYPE
FL_ADDR[9] <= Selector43.DB_MAX_OUTPUT_PORT_TYPE
FL_ADDR[10] <= Selector42.DB_MAX_OUTPUT_PORT_TYPE
FL_ADDR[11] <= Selector41.DB_MAX_OUTPUT_PORT_TYPE
FL_ADDR[12] <= Selector40.DB_MAX_OUTPUT_PORT_TYPE
FL_ADDR[13] <= Selector39.DB_MAX_OUTPUT_PORT_TYPE
FL_ADDR[14] <= Selector38.DB_MAX_OUTPUT_PORT_TYPE
FL_ADDR[15] <= Selector37.DB_MAX_OUTPUT_PORT_TYPE
FL_ADDR[16] <= Selector36.DB_MAX_OUTPUT_PORT_TYPE
FL_ADDR[17] <= Selector35.DB_MAX_OUTPUT_PORT_TYPE
FL_ADDR[18] <= Selector34.DB_MAX_OUTPUT_PORT_TYPE
FL_ADDR[19] <= Selector33.DB_MAX_OUTPUT_PORT_TYPE
FL_ADDR[20] <= Selector32.DB_MAX_OUTPUT_PORT_TYPE
FL_ADDR[21] <= Selector31.DB_MAX_OUTPUT_PORT_TYPE
FL_WE_n <= FL_WE_n~1.DB_MAX_OUTPUT_PORT_TYPE
FL_CE_n <= ST.IDEL.DB_MAX_OUTPUT_PORT_TYPE
FL_OE_n <= ST.READ.DB_MAX_OUTPUT_PORT_TYPE
FL_RST_n <= ST.RESET.DB_MAX_OUTPUT_PORT_TYPE


|DE2_USB_API|Multi_Sdram:u3
oHS_DATA[0] <= Sdram_Multiplexer:u0.port0
oHS_DATA[1] <= Sdram_Multiplexer:u0.port0
oHS_DATA[2] <= Sdram_Multiplexer:u0.port0
oHS_DATA[3] <= Sdram_Multiplexer:u0.port0
oHS_DATA[4] <= Sdram_Multiplexer:u0.port0
oHS_DATA[5] <= Sdram_Multiplexer:u0.port0
oHS_DATA[6] <= Sdram_Multiplexer:u0.port0
oHS_DATA[7] <= Sdram_Multiplexer:u0.port0
oHS_DATA[8] <= Sdram_Multiplexer:u0.port0
oHS_DATA[9] <= Sdram_Multiplexer:u0.port0
oHS_DATA[10] <= Sdram_Multiplexer:u0.port0
oHS_DATA[11] <= Sdram_Multiplexer:u0.port0
oHS_DATA[12] <= Sdram_Multiplexer:u0.port0
oHS_DATA[13] <= Sdram_Multiplexer:u0.port0
oHS_DATA[14] <= Sdram_Multiplexer:u0.port0
oHS_DATA[15] <= Sdram_Multiplexer:u0.port0
iHS_DATA[0] => iHS_DATA[0]~15.IN1
iHS_DATA[1] => iHS_DATA[1]~14.IN1
iHS_DATA[2] => iHS_DATA[2]~13.IN1
iHS_DATA[3] => iHS_DATA[3]~12.IN1
iHS_DATA[4] => iHS_DATA[4]~11.IN1
iHS_DATA[5] => iHS_DATA[5]~10.IN1
iHS_DATA[6] => iHS_DATA[6]~9.IN1
iHS_DATA[7] => iHS_DATA[7]~8.IN1
iHS_DATA[8] => iHS_DATA[8]~7.IN1
iHS_DATA[9] => iHS_DATA[9]~6.IN1
iHS_DATA[10] => iHS_DATA[10]~5.IN1
iHS_DATA[11] => iHS_DATA[11]~4.IN1
iHS_DATA[12] => iHS_DATA[12]~3.IN1
iHS_DATA[13] => iHS_DATA[13]~2.IN1
iHS_DATA[14] => iHS_DATA[14]~1.IN1
iHS_DATA[15] => iHS_DATA[15]~0.IN1
iHS_ADDR[0] => iHS_ADDR[0]~21.IN1
iHS_ADDR[1] => iHS_ADDR[1]~20.IN1
iHS_ADDR[2] => iHS_ADDR[2]~19.IN1
iHS_ADDR[3] => iHS_ADDR[3]~18.IN1
iHS_ADDR[4] => iHS_ADDR[4]~17.IN1
iHS_ADDR[5] => iHS_ADDR[5]~16.IN1
iHS_ADDR[6] => iHS_ADDR[6]~15.IN1
iHS_ADDR[7] => iHS_ADDR[7]~14.IN1
iHS_ADDR[8] => iHS_ADDR[8]~13.IN1
iHS_ADDR[9] => iHS_ADDR[9]~12.IN1
iHS_ADDR[10] => iHS_ADDR[10]~11.IN1
iHS_ADDR[11] => iHS_ADDR[11]~10.IN1
iHS_ADDR[12] => iHS_ADDR[12]~9.IN1
iHS_ADDR[13] => iHS_ADDR[13]~8.IN1
iHS_ADDR[14] => iHS_ADDR[14]~7.IN1
iHS_ADDR[15] => iHS_ADDR[15]~6.IN1
iHS_ADDR[16] => iHS_ADDR[16]~5.IN1
iHS_ADDR[17] => iHS_ADDR[17]~4.IN1
iHS_ADDR[18] => iHS_ADDR[18]~3.IN1
iHS_ADDR[19] => iHS_ADDR[19]~2.IN1
iHS_ADDR[20] => iHS_ADDR[20]~1.IN1
iHS_ADDR[21] => iHS_ADDR[21]~0.IN1
iHS_RD => iHS_RD~0.IN1
iHS_WR => iHS_WR~0.IN1
oHS_Done <= Sdram_Multiplexer:u0.port5
oAS1_DATA[0] <= Sdram_Multiplexer:u0.port6
oAS1_DATA[1] <= Sdram_Multiplexer:u0.port6
oAS1_DATA[2] <= Sdram_Multiplexer:u0.port6
oAS1_DATA[3] <= Sdram_Multiplexer:u0.port6
oAS1_DATA[4] <= Sdram_Multiplexer:u0.port6
oAS1_DATA[5] <= Sdram_Multiplexer:u0.port6
oAS1_DATA[6] <= Sdram_Multiplexer:u0.port6
oAS1_DATA[7] <= Sdram_Multiplexer:u0.port6
oAS1_DATA[8] <= Sdram_Multiplexer:u0.port6
oAS1_DATA[9] <= Sdram_Multiplexer:u0.port6
oAS1_DATA[10] <= Sdram_Multiplexer:u0.port6
oAS1_DATA[11] <= Sdram_Multiplexer:u0.port6
oAS1_DATA[12] <= Sdram_Multiplexer:u0.port6
oAS1_DATA[13] <= Sdram_Multiplexer:u0.port6
oAS1_DATA[14] <= Sdram_Multiplexer:u0.port6
oAS1_DATA[15] <= Sdram_Multiplexer:u0.port6
iAS1_DATA[0] => iAS1_DATA[0]~15.IN1
iAS1_DATA[1] => iAS1_DATA[1]~14.IN1
iAS1_DATA[2] => iAS1_DATA[2]~13.IN1
iAS1_DATA[3] => iAS1_DATA[3]~12.IN1
iAS1_DATA[4] => iAS1_DATA[4]~11.IN1
iAS1_DATA[5] => iAS1_DATA[5]~10.IN1