de2_usb_api.hier_info

Altera de2开发板提供的配套软件程序

|DE2_USB_API
OSC_27 => OSC_27~0.IN1
OSC_50 => OSC_50~0.IN8
EXT_CLOCK => ~NO_FANOUT~
KEY[0] => KEY[0]~0.IN7
KEY[1] => ~NO_FANOUT~
KEY[2] => ~NO_FANOUT~
KEY[3] => ~NO_FANOUT~
DPDT_SW[0] => DPDT_SW[0]~1.IN1
DPDT_SW[1] => DPDT_SW[1]~0.IN1
DPDT_SW[2] => ~NO_FANOUT~
DPDT_SW[3] => ~NO_FANOUT~
DPDT_SW[4] => ~NO_FANOUT~
DPDT_SW[5] => ~NO_FANOUT~
DPDT_SW[6] => ~NO_FANOUT~
DPDT_SW[7] => ~NO_FANOUT~
DPDT_SW[8] => ~NO_FANOUT~
DPDT_SW[9] => ~NO_FANOUT~
DPDT_SW[10] => ~NO_FANOUT~
DPDT_SW[11] => ~NO_FANOUT~
DPDT_SW[12] => ~NO_FANOUT~
DPDT_SW[13] => ~NO_FANOUT~
DPDT_SW[14] => ~NO_FANOUT~
DPDT_SW[15] => ~NO_FANOUT~
DPDT_SW[16] => ~NO_FANOUT~
DPDT_SW[17] => ~NO_FANOUT~
HEX0[0] <= SEG7_LUT_8:u0.port0
HEX0[1] <= SEG7_LUT_8:u0.port0
HEX0[2] <= SEG7_LUT_8:u0.port0
HEX0[3] <= SEG7_LUT_8:u0.port0
HEX0[4] <= SEG7_LUT_8:u0.port0
HEX0[5] <= SEG7_LUT_8:u0.port0
HEX0[6] <= SEG7_LUT_8:u0.port0
HEX1[0] <= SEG7_LUT_8:u0.port1
HEX1[1] <= SEG7_LUT_8:u0.port1
HEX1[2] <= SEG7_LUT_8:u0.port1
HEX1[3] <= SEG7_LUT_8:u0.port1
HEX1[4] <= SEG7_LUT_8:u0.port1
HEX1[5] <= SEG7_LUT_8:u0.port1
HEX1[6] <= SEG7_LUT_8:u0.port1
HEX2[0] <= SEG7_LUT_8:u0.port2
HEX2[1] <= SEG7_LUT_8:u0.port2
HEX2[2] <= SEG7_LUT_8:u0.port2
HEX2[3] <= SEG7_LUT_8:u0.port2
HEX2[4] <= SEG7_LUT_8:u0.port2
HEX2[5] <= SEG7_LUT_8:u0.port2
HEX2[6] <= SEG7_LUT_8:u0.port2
HEX3[0] <= SEG7_LUT_8:u0.port3
HEX3[1] <= SEG7_LUT_8:u0.port3
HEX3[2] <= SEG7_LUT_8:u0.port3
HEX3[3] <= SEG7_LUT_8:u0.port3
HEX3[4] <= SEG7_LUT_8:u0.port3
HEX3[5] <= SEG7_LUT_8:u0.port3
HEX3[6] <= SEG7_LUT_8:u0.port3
HEX4[0] <= SEG7_LUT_8:u0.port4
HEX4[1] <= SEG7_LUT_8:u0.port4
HEX4[2] <= SEG7_LUT_8:u0.port4
HEX4[3] <= SEG7_LUT_8:u0.port4
HEX4[4] <= SEG7_LUT_8:u0.port4
HEX4[5] <= SEG7_LUT_8:u0.port4
HEX4[6] <= SEG7_LUT_8:u0.port4
HEX5[0] <= SEG7_LUT_8:u0.port5
HEX5[1] <= SEG7_LUT_8:u0.port5
HEX5[2] <= SEG7_LUT_8:u0.port5
HEX5[3] <= SEG7_LUT_8:u0.port5
HEX5[4] <= SEG7_LUT_8:u0.port5
HEX5[5] <= SEG7_LUT_8:u0.port5
HEX5[6] <= SEG7_LUT_8:u0.port5
HEX6[0] <= SEG7_LUT_8:u0.port6
HEX6[1] <= SEG7_LUT_8:u0.port6
HEX6[2] <= SEG7_LUT_8:u0.port6
HEX6[3] <= SEG7_LUT_8:u0.port6
HEX6[4] <= SEG7_LUT_8:u0.port6
HEX6[5] <= SEG7_LUT_8:u0.port6
HEX6[6] <= SEG7_LUT_8:u0.port6
HEX7[0] <= SEG7_LUT_8:u0.port7
HEX7[1] <= SEG7_LUT_8:u0.port7
HEX7[2] <= SEG7_LUT_8:u0.port7
HEX7[3] <= SEG7_LUT_8:u0.port7
HEX7[4] <= SEG7_LUT_8:u0.port7
HEX7[5] <= SEG7_LUT_8:u0.port7
HEX7[6] <= SEG7_LUT_8:u0.port7
LEDG[0] <= CMD_Decode:u5.oLED_GREEN
LEDG[1] <= CMD_Decode:u5.oLED_GREEN
LEDG[2] <= CMD_Decode:u5.oLED_GREEN
LEDG[3] <= CMD_Decode:u5.oLED_GREEN
LEDG[4] <= CMD_Decode:u5.oLED_GREEN
LEDG[5] <= CMD_Decode:u5.oLED_GREEN
LEDG[6] <= CMD_Decode:u5.oLED_GREEN
LEDG[7] <= CMD_Decode:u5.oLED_GREEN
LEDG[8] <= CMD_Decode:u5.oLED_GREEN
LEDR[0] <= CMD_Decode:u5.oLED_RED
LEDR[1] <= CMD_Decode:u5.oLED_RED
LEDR[2] <= CMD_Decode:u5.oLED_RED
LEDR[3] <= CMD_Decode:u5.oLED_RED
LEDR[4] <= CMD_Decode:u5.oLED_RED
LEDR[5] <= CMD_Decode:u5.oLED_RED
LEDR[6] <= CMD_Decode:u5.oLED_RED
LEDR[7] <= CMD_Decode:u5.oLED_RED
LEDR[8] <= CMD_Decode:u5.oLED_RED
LEDR[9] <= CMD_Decode:u5.oLED_RED
LEDR[10] <= CMD_Decode:u5.oLED_RED
LEDR[11] <= CMD_Decode:u5.oLED_RED
LEDR[12] <= CMD_Decode:u5.oLED_RED
LEDR[13] <= CMD_Decode:u5.oLED_RED
LEDR[14] <= CMD_Decode:u5.oLED_RED
LEDR[15] <= CMD_Decode:u5.oLED_RED
LEDR[16] <= CMD_Decode:u5.oLED_RED
LEDR[17] <= CMD_Decode:u5.oLED_RED
UART_TXD <= <GND>
UART_RXD => ~NO_FANOUT~
IRDA_TXD <= <GND>
IRDA_RXD => ~NO_FANOUT~
DRAM_DQ[0] <= Multi_Sdram:u3.port28
DRAM_DQ[1] <= Multi_Sdram:u3.port28
DRAM_DQ[2] <= Multi_Sdram:u3.port28
DRAM_DQ[3] <= Multi_Sdram:u3.port28
DRAM_DQ[4] <= Multi_Sdram:u3.port28
DRAM_DQ[5] <= Multi_Sdram:u3.port28
DRAM_DQ[6] <= Multi_Sdram:u3.port28
DRAM_DQ[7] <= Multi_Sdram:u3.port28
DRAM_DQ[8] <= Multi_Sdram:u3.port28
DRAM_DQ[9] <= Multi_Sdram:u3.port28
DRAM_DQ[10] <= Multi_Sdram:u3.port28
DRAM_DQ[11] <= Multi_Sdram:u3.port28
DRAM_DQ[12] <= Multi_Sdram:u3.port28
DRAM_DQ[13] <= Multi_Sdram:u3.port28
DRAM_DQ[14] <= Multi_Sdram:u3.port28
DRAM_DQ[15] <= Multi_Sdram:u3.port28
DRAM_ADDR[0] <= Multi_Sdram:u3.port21
DRAM_ADDR[1] <= Multi_Sdram:u3.port21
DRAM_ADDR[2] <= Multi_Sdram:u3.port21
DRAM_ADDR[3] <= Multi_Sdram:u3.port21
DRAM_ADDR[4] <= Multi_Sdram:u3.port21
DRAM_ADDR[5] <= Multi_Sdram:u3.port21
DRAM_ADDR[6] <= Multi_Sdram:u3.port21
DRAM_ADDR[7] <= Multi_Sdram:u3.port21
DRAM_ADDR[8] <= Multi_Sdram:u3.port21
DRAM_ADDR[9] <= Multi_Sdram:u3.port21
DRAM_ADDR[10] <= Multi_Sdram:u3.port21
DRAM_ADDR[11] <= Multi_Sdram:u3.port21
DRAM_LDQM <= Multi_Sdram:u3.port29
DRAM_UDQM <= Multi_Sdram:u3.port29
DRAM_WE_N <= Multi_Sdram:u3.port27
DRAM_CAS_N <= Multi_Sdram:u3.port26
DRAM_RAS_N <= Multi_Sdram:u3.port25
DRAM_CS_N <= Multi_Sdram:u3.port23
DRAM_BA_0 <= Multi_Sdram:u3.port22
DRAM_BA_1 <= Multi_Sdram:u3.port22
DRAM_CLK <= Multi_Sdram:u3.port30
DRAM_CKE <= Multi_Sdram:u3.port24
FL_DQ[0] <= Multi_Flash:u2.port15
FL_DQ[1] <= Multi_Flash:u2.port15
FL_DQ[2] <= Multi_Flash:u2.port15
FL_DQ[3] <= Multi_Flash:u2.port15
FL_DQ[4] <= Multi_Flash:u2.port15
FL_DQ[5] <= Multi_Flash:u2.port15
FL_DQ[6] <= Multi_Flash:u2.port15
FL_DQ[7] <= Multi_Flash:u2.port15
FL_ADDR[0] <= Multi_Flash:u2.port16
FL_ADDR[1] <= Multi_Flash:u2.port16
FL_ADDR[2] <= Multi_Flash:u2.port16
FL_ADDR[3] <= Multi_Flash:u2.port16
FL_ADDR[4] <= Multi_Flash:u2.port16
FL_ADDR[5] <= Multi_Flash:u2.port16
FL_ADDR[6] <= Multi_Flash:u2.port16
FL_ADDR[7] <= Multi_Flash:u2.port16
FL_ADDR[8] <= Multi_Flash:u2.port16
FL_ADDR[9] <= Multi_Flash:u2.port16
FL_ADDR[10] <= Multi_Flash:u2.port16
FL_ADDR[11] <= Multi_Flash:u2.port16
FL_ADDR[12] <= Multi_Flash:u2.port16
FL_ADDR[13] <= Multi_Flash:u2.port16
FL_ADDR[14] <= Multi_Flash:u2.port16
FL_ADDR[15] <= Multi_Flash:u2.port16
FL_ADDR[16] <= Multi_Flash:u2.port16
FL_ADDR[17] <= Multi_Flash:u2.port16
FL_ADDR[18] <= Multi_Flash:u2.port16
FL_ADDR[19] <= Multi_Flash:u2.port16
FL_ADDR[20] <= Multi_Flash:u2.port16
FL_ADDR[21] <= Multi_Flash:u2.port16
FL_WE_N <= Multi_Flash:u2.port17
FL_RST_N <= Multi_Flash:u2.port20
FL_OE_N <= Multi_Flash:u2.port19
FL_CE_N <= Multi_Flash:u2.port18
SRAM_DQ[0] <= Multi_Sram:u6.SRAM_DQ
SRAM_DQ[1] <= Multi_Sram:u6.SRAM_DQ
SRAM_DQ[2] <= Multi_Sram:u6.SRAM_DQ
SRAM_DQ[3] <= Multi_Sram:u6.SRAM_DQ
SRAM_DQ[4] <= Multi_Sram:u6.SRAM_DQ
SRAM_DQ[5] <= Multi_Sram:u6.SRAM_DQ
SRAM_DQ[6] <= Multi_Sram:u6.SRAM_DQ
SRAM_DQ[7] <= Multi_Sram:u6.SRAM_DQ
SRAM_DQ[8] <= Multi_Sram:u6.SRAM_DQ
SRAM_DQ[9] <= Multi_Sram:u6.SRAM_DQ
SRAM_DQ[10] <= Multi_Sram:u6.SRAM_DQ
SRAM_DQ[11] <= Multi_Sram:u6.SRAM_DQ
SRAM_DQ[12] <= Multi_Sram:u6.SRAM_DQ
SRAM_DQ[13] <= Multi_Sram:u6.SRAM_DQ
SRAM_DQ[14] <= Multi_Sram:u6.SRAM_DQ
SRAM_DQ[15] <= Multi_Sram:u6.SRAM_DQ
SRAM_ADDR[0] <= Multi_Sram:u6.SRAM_ADDR
SRAM_ADDR[1] <= Multi_Sram:u6.SRAM_ADDR
SRAM_ADDR[2] <= Multi_Sram:u6.SRAM_ADDR
SRAM_ADDR[3] <= Multi_Sram:u6.SRAM_ADDR
SRAM_ADDR[4] <= Multi_Sram:u6.SRAM_ADDR
SRAM_ADDR[5] <= Multi_Sram:u6.SRAM_ADDR
SRAM_ADDR[6] <= Multi_Sram:u6.SRAM_ADDR
SRAM_ADDR[7] <= Multi_Sram:u6.SRAM_ADDR
SRAM_ADDR[8] <= Multi_Sram:u6.SRAM_ADDR
SRAM_ADDR[9] <= Multi_Sram:u6.SRAM_ADDR
SRAM_ADDR[10] <= Multi_Sram:u6.SRAM_ADDR
SRAM_ADDR[11] <= Multi_Sram:u6.SRAM_ADDR
SRAM_ADDR[12] <= Multi_Sram:u6.SRAM_ADDR
SRAM_ADDR[13] <= Multi_Sram:u6.SRAM_ADDR
SRAM_ADDR[14] <= Multi_Sram:u6.SRAM_ADDR
SRAM_ADDR[15] <= Multi_Sram:u6.SRAM_ADDR
SRAM_ADDR[16] <= Multi_Sram:u6.SRAM_ADDR
SRAM_ADDR[17] <= Multi_Sram:u6.SRAM_ADDR
SRAM_UB_N <= Multi_Sram:u6.SRAM_UB_N
SRAM_LB_N <= Multi_Sram:u6.SRAM_LB_N
SRAM_WE_N <= Multi_Sram:u6.SRAM_WE_N
SRAM_CE_N <= Multi_Sram:u6.SRAM_CE_N
SRAM_OE_N <= Multi_Sram:u6.SRAM_OE_N
OTG_DATA[0] <= OTG_DATA~32
OTG_DATA[1] <= OTG_DATA~31
OTG_DATA[2] <= OTG_DATA~30
OTG_DATA[3] <= OTG_DATA~29
OTG_DATA[4] <= OTG_DATA~28
OTG_DATA[5] <= OTG_DATA~27
OTG_DATA[6] <= OTG_DATA~26
OTG_DATA[7] <= OTG_DATA~25
OTG_DATA[8] <= OTG_DATA~24
OTG_DATA[9] <= OTG_DATA~23
OTG_DATA[10] <= OTG_DATA~22
OTG_DATA[11] <= OTG_DATA~21
OTG_DATA[12] <= OTG_DATA~20
OTG_DATA[13] <= OTG_DATA~19
OTG_DATA[14] <= OTG_DATA~18
OTG_DATA[15] <= OTG_DATA~17
OTG_ADDR[0] <= <GND>
OTG_ADDR[1] <= <GND>
OTG_CS_N <= <GND>
OTG_RD_N <= <GND>
OTG_WR_N <= <GND>
OTG_RST_N <= <GND>
OTG_FSPEED <= <GND>
OTG_LSPEED <= <GND>
OTG_INT0 <= <GND>
OTG_INT1 <= <GND>
OTG_DREQ0 <= <GND>
OTG_DREQ1 <= <GND>
OTG_DACK0_N <= <GND>
OTG_DACK1_N <= <GND>
LCD_ON <= <VCC>
LCD_BLON <= <VCC>
LCD_RW <= LCD_Controller:u7.LCD_RW
LCD_EN <= LCD_Controller:u7.LCD_EN
LCD_RS <= LCD_Controller:u7.LCD_RS
LCD_DATA[0] <= LCD_Controller:u7.LCD_DATA
LCD_DATA[1] <= LCD_Controller:u7.LCD_DATA
LCD_DATA[2] <= LCD_Controller:u7.LCD_DATA
LCD_DATA[3] <= LCD_Controller:u7.LCD_DATA
LCD_DATA[4] <= LCD_Controller:u7.LCD_DATA
LCD_DATA[5] <= LCD_Controller:u7.LCD_DATA
LCD_DATA[6] <= LCD_Controller:u7.LCD_DATA
LCD_DATA[7] <= LCD_Controller:u7.LCD_DATA
SD_DAT <= SD_DAT~0
SD_DAT3 <= <UNC>
SD_CMD <= <UNC>
SD_CLK <= <GND>
TDI => TDI~0.IN1
TCK => TCK~0.IN1
TCS => TCS~0.IN1
TDO <= USB_JTAG:u1.TDO
I2C_SDAT <= I2C_AV_Config:u10.I2C_SDAT
I2C_SCLK <= I2C_AV_Config:u10.I2C_SCLK
PS2_DAT => PS2_DAT~0.IN1
PS2_CLK => PS2_CLK~0.IN1
VGA_CLK <= VGA_CLK~0.DB_MAX_OUTPUT_PORT_TYPE
VGA_HS <= VGA_Controller:u8.oVGA_H_SYNC
VGA_VS <= VGA_Controller:u8.oVGA_V_SYNC
VGA_BLANK <= VGA_Controller:u8.oVGA_BLANK
VGA_SYNC <= VGA_Controller:u8.oVGA_SYNC
VGA_R[0] <= VGA_Controller:u8.oVGA_R
VGA_R[1] <= VGA_Controller:u8.oVGA_R
VGA_R[2] <= VGA_Controller:u8.oVGA_R
VGA_R[3] <= VGA_Controller:u8.oVGA_R
VGA_R[4] <= VGA_Controller:u8.oVGA_R
VGA_R[5] <= VGA_Controller:u8.oVGA_R
VGA_R[6] <= VGA_Controller:u8.oVGA_R
VGA_R[7] <= VGA_Controller:u8.oVGA_R
VGA_R[8] <= VGA_Controller:u8.oVGA_R
VGA_R[9] <= VGA_Controller:u8.oVGA_R
VGA_G[0] <= VGA_Controller:u8.oVGA_G
VGA_G[1] <= VGA_Controller:u8.oVGA_G
VGA_G[2] <= VGA_Controller:u8.oVGA_G
VGA_G[3] <= VGA_Controller:u8.oVGA_G
VGA_G[4] <= VGA_Controller:u8.oVGA_G
VGA_G[5] <= VGA_Controller:u8.oVGA_G
VGA_G[6] <= VGA_Controller:u8.oVGA_G
VGA_G[7] <= VGA_Controller:u8.oVGA_G
VGA_G[8] <= VGA_Controller:u8.oVGA_G
VGA_G[9] <= VGA_Controller:u8.oVGA_G
VGA_B[0] <= VGA_Controller:u8.oVGA_B
VGA_B[1] <= VGA_Controller:u8.oVGA_B
VGA_B[2] <= VGA_Controller:u8.oVGA_B
VGA_B[3] <= VGA_Controller:u8.oVGA_B
VGA_B[4] <= VGA_Controller:u8.oVGA_B
VGA_B[5] <= VGA_Controller:u8.oVGA_B
VGA_B[6] <= VGA_Controller:u8.oVGA_B
VGA_B[7] <= VGA_Controller:u8.oVGA_B
VGA_B[8] <= VGA_Controller:u8.oVGA_B
VGA_B[9] <= VGA_Controller:u8.oVGA_B
ENET_DATA[0] <= ENET_DATA~31
ENET_DATA[1] <= ENET_DATA~30
ENET_DATA[2] <= ENET_DATA~29
ENET_DATA[3] <= ENET_DATA~28
ENET_DATA[4] <= ENET_DATA~27
ENET_DATA[5] <= ENET_DATA~26
ENET_DATA[6] <= ENET_DATA~25
ENET_DATA[7] <= ENET_DATA~24
ENET_DATA[8] <= ENET_DATA~23
ENET_DATA[9] <= ENET_DATA~22
ENET_DATA[10] <= ENET_DATA~21
ENET_DATA[11] <= ENET_DATA~20
ENET_DATA[12] <= ENET_DATA~19
ENET_DATA[13] <= ENET_DATA~18
ENET_DATA[14] <= ENET_DATA~17
ENET_DATA[15] <= ENET_DATA~16
ENET_CMD <= <GND>
ENET_CS_N <= <GND>
ENET_WR_N <= <GND>
ENET_RD_N <= <GND>
ENET_RST_N <= <GND>
ENET_INT => ~NO_FANOUT~
ENET_CLK <= <GND>
AUD_ADCLRCK <= AUD_ADCLRCK~0.DB_MAX_OUTPUT_PORT_TYPE
AUD_ADCDAT => ~NO_FANOUT~
AUD_DACLRCK <= AUDIO_DAC:u11.oAUD_LRCK
AUD_DACDAT <= AUDIO_DAC:u11.oAUD_DATA
AUD_BCLK <= AUDIO_DAC:u11.oAUD_BCK
AUD_XCK <= AUD_CTRL_CLK.DB_MAX_OUTPUT_PORT_TYPE
TD_DATA[0] => ~NO_FANOUT~
TD_DATA[1] => ~NO_FANOUT~
TD_DATA[2] => ~NO_FANOUT~
TD_DATA[3] => ~NO_FANOUT~
TD_DATA[4] => ~NO_FANOUT~
TD_DATA[5] => ~NO_FANOUT~
TD_DATA[6] => ~NO_FANOUT~
TD_DATA[7] => ~NO_FANOUT~
TD_HS => ~NO_FANOUT~
TD_VS => ~NO_FANOUT~
TD_RESET <= <VCC>
GPIO_0[0] <= GPIO_0~71
GPIO_0[1] <= GPIO_0~70
GPIO_0[2] <= GPIO_0~69
GPIO_0[3] <= GPIO_0~68
GPIO_0[4] <= GPIO_0~67
GPIO_0[5] <= GPIO_0~66
GPIO_0[6] <= GPIO_0~65
GPIO_0[7] <= GPIO_0~64
GPIO_0[8] <= GPIO_0~63
GPIO_0[9] <= GPIO_0~62
GPIO_0[10] <= GPIO_0~61
GPIO_0[11] <= GPIO_0~60
GPIO_0[12] <= GPIO_0~59
GPIO_0[13] <= GPIO_0~58
GPIO_0[14] <= GPIO_0~57
GPIO_0[15] <= GPIO_0~56
GPIO_0[16] <= GPIO_0~55
GPIO_0[17] <= GPIO_0~54
GPIO_0[18] <= GPIO_0~53
GPIO_0[19] <= GPIO_0~52
GPIO_0[20] <= GPIO_0~51
GPIO_0[21] <= GPIO_0~50
GPIO_0[22] <= GPIO_0~49
GPIO_0[23] <= GPIO_0~48
GPIO_0[24] <= GPIO_0~47
GPIO_0[25] <= GPIO_0~46
GPIO_0[26] <= GPIO_0~45