de2_usb_api.map.qmsg

Altera de2开发板提供的配套软件程序

{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "oe1 command.v(81) " "Info (10041): Verilog HDL or VHDL info at command.v(81): inferred latch for \"oe1\"" {  } { { "Multi_Sdram/command.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/command.v" 81 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "oe2 command.v(239) " "Warning (10240): Verilog HDL Always Construct warning at command.v(239): inferring latch(es) for variable \"oe2\", which holds its previous value in one or more paths through the always construct" {  } { { "Multi_Sdram/command.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/command.v" 239 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "oe2 command.v(82) " "Info (10041): Verilog HDL or VHDL info at command.v(82): inferred latch for \"oe2\"" {  } { { "Multi_Sdram/command.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/command.v" 82 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdr_data_path Multi_Sdram:u3\|Sdram_Controller:u1\|sdr_data_path:data_path1 " "Info: Elaborating entity \"sdr_data_path\" for hierarchy \"Multi_Sdram:u3\|Sdram_Controller:u1\|sdr_data_path:data_path1\"" {  } { { "Multi_Sdram/Sdram_Controller.v" "data_path1" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Controller.v" 163 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "INIT_PER Sdram_Params.h(42) " "Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(42): object \"INIT_PER\" assigned a value but never read" {  } { { "Multi_Sdram/Sdram_Params.h" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Params.h" 42 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "REF_PER Sdram_Params.h(43) " "Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(43): object \"REF_PER\" assigned a value but never read" {  } { { "Multi_Sdram/Sdram_Params.h" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Params.h" 43 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "SC_RCD Sdram_Params.h(45) " "Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(45): object \"SC_RCD\" assigned a value but never read" {  } { { "Multi_Sdram/Sdram_Params.h" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Params.h" 45 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "SC_RRD Sdram_Params.h(46) " "Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(46): object \"SC_RRD\" assigned a value but never read" {  } { { "Multi_Sdram/Sdram_Params.h" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Params.h" 46 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "SDR_BL Sdram_Params.h(53) " "Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(53): object \"SDR_BL\" assigned a value but never read" {  } { { "Multi_Sdram/Sdram_Params.h" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Params.h" 53 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "SDR_BT Sdram_Params.h(58) " "Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(58): object \"SDR_BT\" assigned a value but never read" {  } { { "Multi_Sdram/Sdram_Params.h" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Params.h" 58 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "SDR_CL Sdram_Params.h(60) " "Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(60): object \"SDR_CL\" assigned a value but never read" {  } { { "Multi_Sdram/Sdram_Params.h" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Params.h" 60 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "DM1 sdr_data_path.v(24) " "Warning (10036): Verilog HDL or VHDL warning at sdr_data_path.v(24): object \"DM1\" assigned a value but never read" {  } { { "Multi_Sdram/sdr_data_path.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/sdr_data_path.v" 24 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "DM1\[1\] sdr_data_path.v(24) " "Info (10041): Verilog HDL or VHDL info at sdr_data_path.v(24): inferred latch for \"DM1\[1\]\"" {  } { { "Multi_Sdram/sdr_data_path.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/sdr_data_path.v" 24 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "DM1\[0\] sdr_data_path.v(24) " "Info (10041): Verilog HDL or VHDL info at sdr_data_path.v(24): inferred latch for \"DM1\[0\]\"" {  } { { "Multi_Sdram/sdr_data_path.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/sdr_data_path.v" 24 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ps2_keyboard ps2_keyboard:u4 " "Info: Elaborating entity \"ps2_keyboard\" for hierarchy \"ps2_keyboard:u4\"" {  } { { "DE2_USB_API.v" "u4" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/DE2_USB_API.v" 444 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ps2_keyboard.v(310) " "Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(310): truncated value with size 32 to match size of target (1)" {  } { { "ps2_keyboard.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/ps2_keyboard.v" 310 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ps2_keyboard.v(321) " "Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(321): truncated value with size 32 to match size of target (1)" {  } { { "ps2_keyboard.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/ps2_keyboard.v" 321 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ps2_keyboard.v(322) " "Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(322): truncated value with size 32 to match size of target (1)" {  } { { "ps2_keyboard.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/ps2_keyboard.v" 322 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ps2_keyboard.v(327) " "Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(327): truncated value with size 32 to match size of target (1)" {  } { { "ps2_keyboard.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/ps2_keyboard.v" 327 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ps2_keyboard.v(328) " "Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(328): truncated value with size 32 to match size of target (1)" {  } { { "ps2_keyboard.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/ps2_keyboard.v" 328 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ps2_keyboard.v(330) " "Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(330): truncated value with size 32 to match size of target (1)" {  } { { "ps2_keyboard.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/ps2_keyboard.v" 330 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 ps2_keyboard.v(348) " "Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(348): truncated value with size 32 to match size of target (4)" {  } { { "ps2_keyboard.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/ps2_keyboard.v" 348 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 ps2_keyboard.v(377) " "Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(377): truncated value with size 32 to match size of target (12)" {  } { { "ps2_keyboard.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/ps2_keyboard.v" 377 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 ps2_keyboard.v(385) " "Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(385): truncated value with size 32 to match size of target (8)" {  } { { "ps2_keyboard.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/ps2_keyboard.v" 385 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CMD_Decode CMD_Decode:u5 " "Info: Elaborating entity \"CMD_Decode\" for hierarchy \"CMD_Decode:u5\"" {  } { { "DE2_USB_API.v" "u5" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/DE2_USB_API.v" 483 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "BURST RS232_Command.h(26) " "Warning (10036): Verilog HDL or VHDL warning at RS232_Command.h(26): object \"BURST\" assigned a value but never read" {  } { { "RS232_Command.h" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/RS232_Command.h" 26 0 0 } }  } 0 1