de2_usb_api.map.qmsg

Altera de2开发板提供的配套软件程序

{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "SDR_BL Sdram_Params.h(53) " "Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(53): object \"SDR_BL\" assigned a value but never read" {  } { { "Multi_Sdram/Sdram_Params.h" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Params.h" 53 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "SDR_BT Sdram_Params.h(58) " "Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(58): object \"SDR_BT\" assigned a value but never read" {  } { { "Multi_Sdram/Sdram_Params.h" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Params.h" 58 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "SDR_CL Sdram_Params.h(60) " "Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(60): object \"SDR_CL\" assigned a value but never read" {  } { { "Multi_Sdram/Sdram_Params.h" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Params.h" 60 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 Sdram_Controller.v(225) " "Warning (10230): Verilog HDL assignment warning at Sdram_Controller.v(225): truncated value with size 32 to match size of target (9)" {  } { { "Multi_Sdram/Sdram_Controller.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Controller.v" 225 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PLL1 Multi_Sdram:u3\|Sdram_Controller:u1\|PLL1:sdram_pll1 " "Info: Elaborating entity \"PLL1\" for hierarchy \"Multi_Sdram:u3\|Sdram_Controller:u1\|PLL1:sdram_pll1\"" {  } { { "Multi_Sdram/Sdram_Controller.v" "sdram_pll1" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Controller.v" 109 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i:/altera/quartus60/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file i:/altera/quartus60/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "i:/altera/quartus60/libraries/megafunctions/altpll.tdf" 365 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll Multi_Sdram:u3\|Sdram_Controller:u1\|PLL1:sdram_pll1\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"Multi_Sdram:u3\|Sdram_Controller:u1\|PLL1:sdram_pll1\|altpll:altpll_component\"" {  } { { "Multi_Sdram/PLL1.v" "altpll_component" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/PLL1.v" 83 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "Multi_Sdram:u3\|Sdram_Controller:u1\|PLL1:sdram_pll1\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"Multi_Sdram:u3\|Sdram_Controller:u1\|PLL1:sdram_pll1\|altpll:altpll_component\"" {  } { { "Multi_Sdram/PLL1.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/PLL1.v" 83 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_interface Multi_Sdram:u3\|Sdram_Controller:u1\|control_interface:control1 " "Info: Elaborating entity \"control_interface\" for hierarchy \"Multi_Sdram:u3\|Sdram_Controller:u1\|control_interface:control1\"" {  } { { "Multi_Sdram/Sdram_Controller.v" "control1" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Controller.v" 128 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "SC_RCD Sdram_Params.h(45) " "Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(45): object \"SC_RCD\" assigned a value but never read" {  } { { "Multi_Sdram/Sdram_Params.h" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Params.h" 45 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "SC_RRD Sdram_Params.h(46) " "Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(46): object \"SC_RRD\" assigned a value but never read" {  } { { "Multi_Sdram/Sdram_Params.h" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Params.h" 46 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "SDR_BL Sdram_Params.h(53) " "Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(53): object \"SDR_BL\" assigned a value but never read" {  } { { "Multi_Sdram/Sdram_Params.h" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Params.h" 53 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "SDR_BT Sdram_Params.h(58) " "Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(58): object \"SDR_BT\" assigned a value but never read" {  } { { "Multi_Sdram/Sdram_Params.h" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Params.h" 58 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "SDR_CL Sdram_Params.h(60) " "Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(60): object \"SDR_CL\" assigned a value but never read" {  } { { "Multi_Sdram/Sdram_Params.h" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Params.h" 60 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 control_interface.v(120) " "Warning (10230): Verilog HDL assignment warning at control_interface.v(120): truncated value with size 32 to match size of target (16)" {  } { { "Multi_Sdram/control_interface.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/control_interface.v" 120 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 control_interface.v(125) " "Warning (10230): Verilog HDL assignment warning at control_interface.v(125): truncated value with size 32 to match size of target (16)" {  } { { "Multi_Sdram/control_interface.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/control_interface.v" 125 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 control_interface.v(150) " "Warning (10230): Verilog HDL assignment warning at control_interface.v(150): truncated value with size 32 to match size of target (16)" {  } { { "Multi_Sdram/control_interface.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/control_interface.v" 150 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "command Multi_Sdram:u3\|Sdram_Controller:u1\|command:command1 " "Info: Elaborating entity \"command\" for hierarchy \"Multi_Sdram:u3\|Sdram_Controller:u1\|command:command1\"" {  } { { "Multi_Sdram/Sdram_Controller.v" "command1" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Controller.v" 154 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "INIT_PER Sdram_Params.h(42) " "Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(42): object \"INIT_PER\" assigned a value but never read" {  } { { "Multi_Sdram/Sdram_Params.h" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Params.h" 42 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "REF_PER Sdram_Params.h(43) " "Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(43): object \"REF_PER\" assigned a value but never read" {  } { { "Multi_Sdram/Sdram_Params.h" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Params.h" 43 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "SC_RRD Sdram_Params.h(46) " "Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(46): object \"SC_RRD\" assigned a value but never read" {  } { { "Multi_Sdram/Sdram_Params.h" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Params.h" 46 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "oe_shift command.v(239) " "Warning (10240): Verilog HDL Always Construct warning at command.v(239): inferring latch(es) for variable \"oe_shift\", which holds its previous value in one or more paths through the always construct" {  } { { "Multi_Sdram/command.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/command.v" 239 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "oe_shift\[6\] command.v(80) " "Info (10041): Verilog HDL or VHDL info at command.v(80): inferred latch for \"oe_shift\[6\]\"" {  } { { "Multi_Sdram/command.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/command.v" 80 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "oe_shift\[5\] command.v(80) " "Info (10041): Verilog HDL or VHDL info at command.v(80): inferred latch for \"oe_shift\[5\]\"" {  } { { "Multi_Sdram/command.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/command.v" 80 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "oe_shift\[4\] command.v(80) " "Info (10041): Verilog HDL or VHDL info at command.v(80): inferred latch for \"oe_shift\[4\]\"" {  } { { "Multi_Sdram/command.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/command.v" 80 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "oe_shift\[3\] command.v(80) " "Info (10041): Verilog HDL or VHDL info at command.v(80): inferred latch for \"oe_shift\[3\]\"" {  } { { "Multi_Sdram/command.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/command.v" 80 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "oe_shift\[2\] command.v(80) " "Info (10041): Verilog HDL or VHDL info at command.v(80): inferred latch for \"oe_shift\[2\]\"" {  } { { "Multi_Sdram/command.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/command.v" 80 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "oe_shift\[1\] command.v(80) " "Info (10041): Verilog HDL or VHDL info at command.v(80): inferred latch for \"oe_shift\[1\]\"" {  } { { "Multi_Sdram/command.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/command.v" 80 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "oe_shift\[0\] command.v(80) " "Info (10041): Verilog HDL or VHDL info at command.v(80): inferred latch for \"oe_shift\[0\]\"" {  } { { "Multi_Sdram/command.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/command.v" 80 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "oe1 command.v(239) " "Warning (10240): Verilog HDL Always Construct warning at command.v(239): inferring latch(es) for variable \"oe1\", which holds its previous value in one or more paths through the always construct" {  } { { "Multi_Sdram/command.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/command.v" 239 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}