de2_usb_api.map.qmsg

Altera de2开发板提供的配套软件程序

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CLK_LOCK CLK_LOCK:p0 " "Info: Elaborating entity \"CLK_LOCK\" for hierarchy \"CLK_LOCK:p0\"" {  } { { "DE2_USB_API.v" "p0" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/DE2_USB_API.v" 402 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CLK_LOCK_altclkctrl_tb8 CLK_LOCK:p0\|CLK_LOCK_altclkctrl_tb8:CLK_LOCK_altclkctrl_tb8_component " "Info: Elaborating entity \"CLK_LOCK_altclkctrl_tb8\" for hierarchy \"CLK_LOCK:p0\|CLK_LOCK_altclkctrl_tb8:CLK_LOCK_altclkctrl_tb8_component\"" {  } { { "CLK_LOCK.v" "CLK_LOCK_altclkctrl_tb8_component" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/CLK_LOCK.v" 97 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Reset_Delay Reset_Delay:d0 " "Info: Elaborating entity \"Reset_Delay\" for hierarchy \"Reset_Delay:d0\"" {  } { { "DE2_USB_API.v" "d0" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/DE2_USB_API.v" 404 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 20 Reset_Delay.v(10) " "Warning (10230): Verilog HDL assignment warning at Reset_Delay.v(10): truncated value with size 32 to match size of target (20)" {  } { { "Reset_Delay.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Reset_Delay.v" 10 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT_8 SEG7_LUT_8:u0 " "Info: Elaborating entity \"SEG7_LUT_8\" for hierarchy \"SEG7_LUT_8:u0\"" {  } { { "DE2_USB_API.v" "u0" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/DE2_USB_API.v" 406 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT SEG7_LUT_8:u0\|SEG7_LUT:u0 " "Info: Elaborating entity \"SEG7_LUT\" for hierarchy \"SEG7_LUT_8:u0\|SEG7_LUT:u0\"" {  } { { "SEG7_LUT_8.v" "u0" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/SEG7_LUT_8.v" 5 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "USB_JTAG USB_JTAG:u1 " "Info: Elaborating entity \"USB_JTAG\" for hierarchy \"USB_JTAG:u1\"" {  } { { "DE2_USB_API.v" "u1" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/DE2_USB_API.v" 412 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "JTAG_REC USB_JTAG:u1\|JTAG_REC:u0 " "Info: Elaborating entity \"JTAG_REC\" for hierarchy \"USB_JTAG:u1\|JTAG_REC:u0\"" {  } { { "USB_JTAG.v" "u0" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/USB_JTAG.v" 19 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 USB_JTAG.v(81) " "Warning (10230): Verilog HDL assignment warning at USB_JTAG.v(81): truncated value with size 32 to match size of target (3)" {  } { { "USB_JTAG.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/USB_JTAG.v" 81 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "JTAG_TRANS USB_JTAG:u1\|JTAG_TRANS:u1 " "Info: Elaborating entity \"JTAG_TRANS\" for hierarchy \"USB_JTAG:u1\|JTAG_TRANS:u1\"" {  } { { "USB_JTAG.v" "u1" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/USB_JTAG.v" 42 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 USB_JTAG.v(116) " "Warning (10230): Verilog HDL assignment warning at USB_JTAG.v(116): truncated value with size 32 to match size of target (3)" {  } { { "USB_JTAG.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/USB_JTAG.v" 116 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Multi_Flash Multi_Flash:u2 " "Info: Elaborating entity \"Multi_Flash\" for hierarchy \"Multi_Flash:u2\"" {  } { { "DE2_USB_API.v" "u2" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/DE2_USB_API.v" 425 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Flash_Multiplexer Multi_Flash:u2\|Flash_Multiplexer:u0 " "Info: Elaborating entity \"Flash_Multiplexer\" for hierarchy \"Multi_Flash:u2\|Flash_Multiplexer:u0\"" {  } { { "Multi_Flash/Multi_Flash.v" "u0" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Flash/Multi_Flash.v" 60 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Flash_Controller Multi_Flash:u2\|Flash_Controller:u1 " "Info: Elaborating entity \"Flash_Controller\" for hierarchy \"Multi_Flash:u2\|Flash_Controller:u1\"" {  } { { "Multi_Flash/Multi_Flash.v" "u1" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Flash/Multi_Flash.v" 66 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 Flash_Controller.v(83) " "Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(83): truncated value with size 32 to match size of target (11)" {  } { { "Multi_Flash/Flash_Controller.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Flash/Flash_Controller.v" 83 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 Flash_Controller.v(132) " "Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(132): truncated value with size 32 to match size of target (11)" {  } { { "Multi_Flash/Flash_Controller.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Flash/Flash_Controller.v" 132 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 Flash_Controller.v(227) " "Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(227): truncated value with size 32 to match size of target (22)" {  } { { "Multi_Flash/Flash_Controller.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Flash/Flash_Controller.v" 227 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 Flash_Controller.v(239) " "Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(239): truncated value with size 32 to match size of target (22)" {  } { { "Multi_Flash/Flash_Controller.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Flash/Flash_Controller.v" 239 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 Flash_Controller.v(240) " "Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(240): truncated value with size 32 to match size of target (22)" {  } { { "Multi_Flash/Flash_Controller.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Flash/Flash_Controller.v" 240 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 Flash_Controller.v(241) " "Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(241): truncated value with size 32 to match size of target (22)" {  } { { "Multi_Flash/Flash_Controller.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Flash/Flash_Controller.v" 241 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 Flash_Controller.v(242) " "Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(242): truncated value with size 32 to match size of target (22)" {  } { { "Multi_Flash/Flash_Controller.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Flash/Flash_Controller.v" 242 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 Flash_Controller.v(243) " "Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(243): truncated value with size 32 to match size of target (22)" {  } { { "Multi_Flash/Flash_Controller.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Flash/Flash_Controller.v" 243 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 Flash_Controller.v(244) " "Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(244): truncated value with size 32 to match size of target (22)" {  } { { "Multi_Flash/Flash_Controller.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Flash/Flash_Controller.v" 244 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 Flash_Controller.v(245) " "Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(245): truncated value with size 32 to match size of target (22)" {  } { { "Multi_Flash/Flash_Controller.v" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Flash/Flash_Controller.v" 245 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Multi_Sdram Multi_Sdram:u3 " "Info: Elaborating entity \"Multi_Sdram\" for hierarchy \"Multi_Sdram:u3\"" {  } { { "DE2_USB_API.v" "u3" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/DE2_USB_API.v" 439 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Sdram_Multiplexer Multi_Sdram:u3\|Sdram_Multiplexer:u0 " "Info: Elaborating entity \"Sdram_Multiplexer\" for hierarchy \"Multi_Sdram:u3\|Sdram_Multiplexer:u0\"" {  } { { "Multi_Sdram/Multi_Sdram.v" "u0" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Multi_Sdram.v" 69 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Sdram_Controller Multi_Sdram:u3\|Sdram_Controller:u1 " "Info: Elaborating entity \"Sdram_Controller\" for hierarchy \"Multi_Sdram:u3\|Sdram_Controller:u1\"" {  } { { "Multi_Sdram/Multi_Sdram.v" "u1" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Multi_Sdram.v" 89 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "INIT_PER Sdram_Params.h(42) " "Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(42): object \"INIT_PER\" assigned a value but never read" {  } { { "Multi_Sdram/Sdram_Params.h" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Params.h" 42 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "REF_PER Sdram_Params.h(43) " "Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(43): object \"REF_PER\" assigned a value but never read" {  } { { "Multi_Sdram/Sdram_Params.h" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Params.h" 43 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "SC_RRD Sdram_Params.h(46) " "Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(46): object \"SC_RRD\" assigned a value but never read" {  } { { "Multi_Sdram/Sdram_Params.h" "" { Text "E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Params.h" 46 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}