📄 de2_usb_api.map.rpt
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; Top-level entity name ; DE2_USB_API ; DE2_USB_API ;
; Family name ; Cyclone II ; Stratix ;
; Use smart compilation ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; Maximum DSP Block Usage ; Unlimited ; Unlimited ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- Cyclone II ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Maximum Number of M4K Memory Blocks ; Unlimited ; Unlimited ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
+--------------------------------------------------------------------+--------------------+--------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------------------------------+
; AUDIO_DAC.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/AUDIO_DAC.v ;
; CLK_LOCK.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/CLK_LOCK.v ;
; CMD_Decode.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/CMD_Decode.v ;
; DE2_USB_API.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/DE2_USB_API.v ;
; I2C_AV_Config.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_AV_Config.v ;
; I2C_Controller.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/I2C_Controller.v ;
; LCD_Controller.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/LCD_Controller.v ;
; Multi_Sram.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sram.v ;
; ps2_keyboard.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/ps2_keyboard.v ;
; Reset_Delay.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Reset_Delay.v ;
; SEG7_LUT.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/SEG7_LUT.v ;
; SEG7_LUT_8.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/SEG7_LUT_8.v ;
; USB_JTAG.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/USB_JTAG.v ;
; VGA_Audio_PLL.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/VGA_Audio_PLL.v ;
; Multi_Flash/Multi_Flash.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Flash/Multi_Flash.v ;
; Multi_Sdram/Sdram_Multiplexer.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Multiplexer.v ;
; Multi_Sdram/Multi_Sdram.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Multi_Sdram.v ;
; Multi_Sdram/Sdram_Controller.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Controller.v ;
; Multi_Flash/Flash_Controller.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Flash/Flash_Controller.v ;
; Multi_Flash/Flash_Multiplexer.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Flash/Flash_Multiplexer.v ;
; Multi_Sdram/sdr_data_path.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/sdr_data_path.v ;
; Multi_Sdram/command.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/command.v ;
; Multi_Sdram/control_interface.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/control_interface.v ;
; Multi_Sdram/PLL1.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/PLL1.v ;
; VGA_Controller/Img_RAM.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/VGA_Controller/Img_RAM.v ;
; VGA_Controller/VGA_Controller.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/VGA_Controller/VGA_Controller.v ;
; VGA_Controller/VGA_OSD_RAM.v ; yes ; User Verilog HDL File ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/VGA_Controller/VGA_OSD_RAM.v ;
; Flash_Command.h ; yes ; Other ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Flash_Command.h ;
; VGA_Controller/VGA_Param.h ; yes ; Other ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/VGA_Controller/VGA_Param.h ;
; Multi_Sdram/Sdram_Params.h ; yes ; Other ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/Multi_Sdram/Sdram_Params.h ;
; RS232_Command.h ; yes ; Other ; E:/chenjian/altera_de2_system/DE2_demonstrations/DE2_USB_API/HW/RS232_Command.h ;
; altpll.tdf ; yes ; Megafunction ; i:/altera/quartus60/libraries/megafunctions/altpll.tdf ;
; aglobal60.inc ; yes ; Other ; i:/altera/quartus60/libraries/megafunctions/aglobal60.inc ;
; stratix_pll.inc ; yes ; Other ; i:/altera/quartus60/libraries/megafunctions/stratix_pll.inc ;
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