📄 vga_audio_pll_waveforms.html
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<title>Sample Waveforms for VGA_Audio_PLL.v </title>
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<h2><CENTER>Sample behavioral waveforms for design file VGA_Audio_PLL.v </CENTER></h2>
<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design VGA_Audio_PLL.v. The design VGA_Audio_PLL.v has Cyclone II FAST pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 37037 ps. CLK0 multiply by = 14, CLK0 divide by = 15, CLK0 phase_shift = 0 CLK1 multiply by = 2, CLK1 divide by = 3, CLK1 phase_shift = 0 Input port ARESET is used. This port is active high. When asserted, it will cause the LOCKED port and all CLK outputs to drop to zero. The PLL will relock to the input clock when this port is deasserted. </P>
<CENTER><img src=VGA_Audio_PLL_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing NORMAL mode operation. </CENTER></P>
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